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full speed usb flash mcu family c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d rev. 1.4 9/09 copyright ? 2009 by silicon laboratories c8051f34x analog peripherals - 10-bit adc (c8051f340/1/2/ 3/4/5/6/7/a/b only) ? up to 200 ksps ? built-in analog multiplexer with single-ended and ? differential mode ? vref from external pin, internal reference, or v dd ? built-in temperature sensor ? external conversion start input option - two comparators - internal voltage reference ? (c8051f340/1/2/3/4/ 5/6/7/a/b o nly) - brown-out detector and por circuitry usb function controller - usb specification 2.0 compliant - full speed (12 mbps) or low speed (1.5 mbps) operation - integrated clock recovery; no external crystal required for full speed or low speed - supports eight flexible endpoints - 1 kb usb buffer memory - integrated transceiver; no external resistors required on-chip debug - on-chip debug circuitry facilitates full speed, non-intru - sive in-system debug (no emulator required) - provides breakpoints, single stepping, ? inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets voltage supply input: 2.7 to 5.25 v - voltages from 3.6 to 5.25 v supported using on-chip ? voltage regulator high speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - 48 mips and 25 mips versions available. - expanded interrupt handler memory - 4352 or 2304 bytes ram - 64 or 32 kb flash; in-system pr ogrammable in 512-by te sectors digital peripherals - 40/25 port i/o; all 5 v tolerant with high sink current - hardware enhanced spi?, smbus?, and one or two en hanced uart serial ports - four general purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with five cap - ture/compare modules - external memory interface (emif) clock sources - internal oscillator: 0.25% accuracy with clock recovery enabled. supports all usb and uart modes - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - low frequency (80 khz) internal oscillator - can switch between cl ock sources on-the-fly packages - 48-pin tqfp (c8051f340/1/4/5/8/c) - 32-pin lqfp (c805 1f342/3/6/7/9/a/b/d) - 5x5 mm 32-pin qfn (c8051f342/3/6/7/9/a/b) temperature range: ?40 to +85 c analog peripherals 10-bit 200 ksps adc 64/32 kb isp flash 4/2 kb ram por debug circuitry flexible interrupts 8051 cpu (48/25 mips) digital i/o precision internal oscillators high-speed controller core a m u x crossbar + - wdt + - usb controller / transceiver port 0 port 1 port 2 port 3 temp sensor vreg vref port 4 ext. memory i/f 48 pin only uart0 smbus pca 4 timers spi uart1* c8051f340/1/2/34/5/6/7/a/b only * c8051f340/1/4/5/8/a/b/c only
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 2 rev. 1.4
rev. 1.3 3 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d table of contents 1. system overview............ ............................................................................. ........... 17 2. absolute maximum ratings ........ ............................................................... ........... 24 3. global dc electrical characteristi cs ...................... ................................. ............. 25 4. pinout and package definitions..... ............... ............................................. ........... 28 5. 10-bit adc (adc0, c8051f340/1/2/3/4/5/6/7/a/b only)... ............................ ......... 41 5.1. analog multiplexer ...... ........................................................................... ........... 42 5.2. temperature sensor ............ .................................................................. ........... 43 5.3. modes of operation ............. .................................................................. ........... 45 5.3.1. starting a conversion....... ............................................................. ........... 45 5.3.2. tracking modes................ ............................................................. ........... 46 5.3.3. settling time r equirements ................ .......................................... ........... 47 5.4. programmable window detector ........................................................... ........... 52 5.4.1. window detector in sing le-ended mode .......... ............................ ........... 54 5.4.2. window detector in differential mode..... .............. ............... ........... ......... 55 6. voltage reference (c8051f340/1/2/3/4/5/6/7/a/b only)................ .............. ......... 57 7. comparators ................ ................................................................................ ........... 59 8. voltage regulator (reg0)......... .................................................................. ........... 69 8.1. regulator mode selectio n................ ........................................................ ......... 69 8.2. vbus detection .......... ........................................................................... ........... 69 9. cip-51 microcontroller .............. .................................................................. ........... 73 9.1. instruction set ........... ............................................................................. ........... 74 9.1.1. instruction and cpu timing .. ........................................................ ........... 74 9.1.2. movx instruction and program memory ... ................................. ............. 75 9.2. memory organization........... .................................................................. ........... 79 9.2.1. program memory.............. ............................................................. ........... 80 9.2.2. data memory........ ......................................................................... ........... 81 9.2.3. general purpose registers ........................................................... ........... 81 9.2.4. bit addressable lo cations.............. ............................................... ........... 81 9.2.5. stack ................. ........................................................................... ........... 81 9.2.6. special function registers. ........................................................... ........... 82 9.2.7. register descriptions ....... ............................................................. ........... 86 9.3. interrupt handler ................ .................................................................. ............. 88 9.3.1. mcu interrupt sources a nd vectors ............ ................................. ........... 88 9.3.2. external interrupts .......... ............................................................... ........... 88 9.3.3. interrupt priorities ........ .................................................................. ........... 89 9.3.4. interrupt latency .............. ............................................................. ........... 89 9.3.5. interrupt register descrip tions.............. .......................................... ......... 90 9.4. power management modes ........... ........................................................ ........... 97 9.4.1. idle mode............ ........................................................................... ........... 97 9.4.2. stop mode ...................... ............................................................... ........... 97 10. prefetch engine ........... ................................................................................ ........... 99 11. reset sources.......... .................................................................................. ........... 100 11.1.power-on reset ....... ............................................................................. ......... 101
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 4 rev. 1.3 11.2.power-fail reset / vd d monitor ................. .......................................... ......... 102 11.3.external reset .......... ............................................................................. ......... 103 11.4.missing clock detector reset ... ............... ............................................. ......... 103 11.5.comparator0 reset ............. .................................................................. ......... 103 11.6.pca watchdog timer reset ..... ............... ............................................. ......... 103 11.7.flash error reset ..... ............................................................................. ......... 103 11.8.software reset ......... ............................................................................. ......... 104 11.9.usb reset................ ............................................................................. ......... 104 12. flash memory ................. ............................................................................. ......... 107 12.1.programming the flash memory .......................................................... ......... 107 12.1.1.flash lock and key functi ons ................ .............. ............... .................. 107 12.1.2.flash erase procedure ...... ........................................................... ......... 107 12.1.3.flash write procedure ..... ............................................................. ......... 108 12.2.non-volatile data st orage................. .................................................. ........... 109 12.3.security options ....... ............................................................................. ......... 109 13. external data memory interface and on-chi p xram............ ................. ........... 114 13.1.accessing xram.......... ......................................................................... ......... 114 13.1.1.16-bit movx example ....... ........................................................... ......... 114 13.1.2.8-bit movx example ......... ........................................................... ......... 114 13.2.accessing usb fifo s pace ....................... .......................................... ......... 115 13.3.configuring the exte rnal memory interface . .......................................... ......... 116 13.4.port configuration..... ............................................................................. ......... 116 13.5.multiplexed and non-multiplex ed selection.......... ................................. ......... 119 13.5.1.multiplexed configuration. ............................................................. ......... 119 13.5.2.non-multiplexed configurat ion.............. ................................................. 120 13.6.memory mode selection...... .................................................................. ......... 120 13.6.1.internal xram only ......... ............................................................. ......... 121 13.6.2.split mode without bank select............. ................................................. 121 13.6.3.split mode with ba nk select................ .......................................... ......... 122 13.6.4.external only...... ........................................................................... ......... 122 13.7.timing ............. .................................................................................. ........... 122 13.7.1.non-multiplexed mode ....... ........................................................... ......... 124 13.7.2.multiplexed mode .... ...................................................................... ......... 127 14. oscillators ................ .................................................................................. ........... 131 14.1.programmable internal hi gh-f requency (h-f) oscillator ... ................. ........... 132 14.1.1.internal h-f oscillator suspend mode ........... ............................... ......... 132 14.2.programmable internal low -frequency (l-f) oscillator .... ................. ........... 133 14.2.1.calibrating the internal l- f oscillator........... ................................. ......... 133 14.3.external oscillator drive circuit................ ............................................. ......... 135 14.3.1.clocking timers direct ly through the exte rnal oscillator.... .................. 135 14.3.2.external crystal example. ............................................................. ......... 135 14.3.3.external rc example....... ............................................................. ......... 136 14.3.4.external capacitor exampl e................ .......................................... ......... 136 14.4.4x clock multiplier .... ............................................................................. ......... 138 14.5.system and usb clock selection ............ ............................................. ......... 139
rev. 1.3 5 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 14.5.1.system clock selection ... ............................................................. ......... 139 14.5.2.usb clock selection ........ ............................................................. ......... 139 15. port input/output............ ............................................................................. ......... 142 15.1.priority crossbar decoder ... .................................................................. ......... 144 15.2.port i/o initialization ........ ...................................................................... ......... 147 15.3.general purpose port i/o .... .................................................................. ......... 150 16. universal serial bus controller (usb0)........... .......................................... ......... 159 16.1.endpoint addressing .... ......................................................................... ......... 160 16.2.usb transceiver ................. .................................................................. ......... 160 16.3.usb register access .......... .................................................................. ......... 162 16.4.usb clock configuration........ ............................................................... ......... 166 16.5.fifo management .......... ...................................................................... ......... 167 16.5.1.fifo split m ode .................... ........................................................ ......... 167 16.5.2.fifo double buffering ....... ........................................................... ......... 168 16.5.3.fifo access ........ ......................................................................... ......... 168 16.6.function addressing............ .................................................................. ......... 169 16.7.function configuration and cont rol ................................................................ 169 16.8.interrupts ........... .................................................................................. ........... 172 16.9.the serial interface engine . .................................................................. ......... 176 16.10.endpoint0 ................. ........................................................................... ......... 176 16.10.1.endpoint0 setup transacti ons .............. ................................. ........... 177 16.10.2.endpoint0 in transactions... ................. .............. ............... .................. 177 16.10.3.endpoint0 out tran sactions................ .............. ............... .................. 178 16.11.configuring endpoints1-3 ....... ............................................................. ......... 180 16.12.controlling endpoi nts1-3 in........... ............................................................... 180 16.12.1.endpoints1-3 in in terrupt or bulk mode .............. ............... .................. 180 16.12.2.endpoints1-3 in isochro nous mode............. ............................... ......... 181 16.13.controlling endpoints1 -3 out............ ................................................. ......... 183 16.13.1.endpoints1-3 out interrupt or bulk mode.......... ............... .................. 183 16.13.2.endpoints1-3 out isochronous mode....... ................................. ......... 184 17. smbus ................. ......................................................................................... ......... 188 17.1.supporting documents ............. ............................................................. ......... 189 17.2.smbus configuration... ............... ........................................................... ......... 189 17.3.smbus operation ....... ........................................................................... ......... 189 17.3.1.arbitration......... ............................................................................. ......... 190 17.3.2.clock low extension........ ............................................................. ......... 191 17.3.3.scl low timeout.... ...................................................................... ......... 191 17.3.4.scl high (smbus free) ti meout .............. ................................. ........... 191 17.4.using the smbus........ ........................................................................... ......... 191 17.4.1.smbus configuration regist er................ .............. ............... .................. 192 17.4.2.smb0cn control register . ........................................................... ......... 195 17.4.3.data register ....... ......................................................................... ......... 198 17.5.smbus transfer modes... ...................................................................... ......... 198 17.5.1.master transmitter mode .. ............... ............................................. ......... 198 17.5.2.master receiver mode .............. .................................................. ........... 200
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 6 rev. 1.3 17.5.3.slave receiver mode ....... ............................................................. ......... 201 17.5.4.slave transmitter mode .... ............... ............................................. ......... 202 17.6.smbus status decoding ........................................................................ ......... 202 18. uart0................ ........................................................................................... ......... 205 18.1.enhanced baud rate g eneration.................. ................................................. 206 18.2.operational modes ....... ......................................................................... ......... 206 18.2.1.8-bit uart ........... ......................................................................... ......... 207 18.2.2.9-bit uart ........... ......................................................................... ......... 208 18.3.multiprocessor communications ... ........................................................ ......... 208 19. uart1 (c8051f340/1/4/5/8/ a/b/c only)............... .............. ............... .................. 213 19.1.baud rate generator ............. ............................................................... ......... 214 19.2.data format......... .................................................................................. ......... 215 19.3.configuration and operat ion ................ ................................................. ......... 216 19.3.1.data transmission ........... ............................................................. ......... 216 19.3.2.data reception .... ......................................................................... ......... 216 19.3.3.multiprocessor communicati ons ................................................... ......... 217 20. enhanced serial peripheral interface (spi0)..... ................................................. 222 20.1.signal descriptions....... ......................................................................... ......... 223 20.1.1.master out, slave in (mos i)...................... ................................. ........... 223 20.1.2.master in, slave out (miso)............... .......................................... ......... 223 20.1.3.serial clock (sck) ........... ............................................................. ......... 223 20.1.4.slave select (nss) .......... ............................................................. ......... 223 20.2.spi0 master mode operation . ............................................................... ......... 224 20.3.spi0 slave mode operation ..... ............................................................. ......... 226 20.4.spi0 interrupt sources ........ .................................................................. ......... 226 20.5.serial clock timing... ............................................................................. ......... 227 20.6.spi special function registers . ............... ............................................. ......... 229 21. timers................ ............................................................ ............... .............. ........... 23 5 21.1.timer 0 and ti mer 1 ............... ............................................................... ......... 235 21.1.1.mode 0: 13-bit counter/timer ................. .............. ............... .................. 235 21.1.2.mode 1: 16-bit counter/timer ................. .............. ............... .................. 236 21.1.3.mode 2: 8-bit counter/tim er with auto-reload.......... ................. ........... 237 21.1.4.mode 3: two 8-bit counter /timers (timer 0 only)..... ................. ........... 238 21.2.timer 2 ............. .................................................................................. ........... 243 21.2.1.16-bit timer with auto-rel oad............... ................................................. 243 21.2.2.8-bit timers with auto-rel oad............... ................................................. 244 21.2.3.timer 2 capture modes: usb start-of-frame or lfo falling edge ...... 245 21.3.timer 3 ............. .................................................................................. ........... 249 21.3.1.16-bit timer with auto-rel oad............... ................................................. 249 21.3.2.8-bit timers with auto-rel oad............... ................................................. 250 21.3.3.usb start-of-frame captur e.................................................................. 251 22. programmable counter array (pca 0) ............... ................................................. 255 22.1.pca counter/timer ............. .................................................................. ......... 256 22.2.capture/compare modules ...... ............................................................. ......... 257 22.2.1.edge-triggered captur e mode................. .............. ............... .................. 258
rev. 1.3 7 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 22.2.2.software timer (compare) mode................. ................................. ......... 259 22.2.3.high speed output mode.............................................................. ......... 260 22.2.4.frequency output mode ....... ........................................................ ......... 261 22.2.5.8-bit pulse width modulato r mode............... ................................. ......... 262 22.2.6.16-bit pulse width modulat or mode............. ................................. ......... 263 22.3.watchdog timer mode .... ...................................................................... ......... 264 22.3.1.watchdog timer operation ... ........................................................ ......... 264 22.3.2.watchdog timer usage ........ ........................................................ ......... 265 22.4.register descriptions for pca. ............... ............................................... ......... 266 23. c2 interface ................ .................................................................................. ......... 271 23.1.c2 interface registers......... .................................................................. ......... 271 23.2.c2 pin sharing ......... ............................................................................. ......... 273 document change list............... ...................................................................... ........ 274 contact information.......... ................................................................................ ........ 276
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 8 rev. 1.3 list of figures 1. system overview figure 1.1. c8051f340/1/ 4/5 block diagram ........ .......................................... ......... 19 figure 1.2. c8051f342/3/ 6/7 block diagram ........ .......................................... ......... 20 figure 1.3. c8051f348/c block diagram.............. .......................................... ......... 21 figure 1.4. c8051f349/d block diagram.............. .......................................... ......... 22 figure 1.5. c8051f34a/b block diagram ........... .......................................... ........... 23 4. pinout and p ackage definitions figure 4.1. tqfp-48 pinout diagram (top view) ............... ............................ ......... 31 figure 4.2. tqfp-48 package diagr am .............. .......................................... ........... 32 figure 4.3. tqfp-48 recomm ended pcb land pattern ........... ................. ............. 33 figure 4.4. lqfp-32 pi nout diagram (top view).............. ............................ ........... 34 figure 4.5. lqfp-32 package diagr am .............. .......................................... ........... 35 figure 4.6. lqfp-32 recomm ended pcb land pattern ........... ................. ............. 36 figure 4.7. qfn-32 pinout diagr am (top view) .......... ................................. ........... 37 5. 10-bit adc (adc 0, c8051f340/1/2/3/ 4/5/6/7/a/b only) figure 5.1. adc0 functional bl ock diagram.............. ................................. ............. 41 figure 5.2. temperature sensor transfer function .............. ............... ........... ......... 43 figure 5.3. temperature sens or error with 1-point calib ration (vref = 2.40 v) .... 44 figure 5.4. 10-bit adc track and conversion exampl e timing ............ ............ ...... 46 figure 5.5. adc0 equivalent i nput circuits ............. .............. ............... ........... ......... 47 figure 5.6. adc window co mpare example: right-justi fied single-ended data ... 54 figure 5.7. adc window co mpare example: left-justif ied single-ended data...... 54 figure 5.8. adc window compar e example: right-justified differential data ........ 55 figure 5.9. adc window com pare example: left-justified differential data .......... 55 6. voltage reference (c8051f3 40/1/2/3/4/5/6/7/a/b only) figure 6.1. voltage reference functional block diagram........ ............ ........... ......... 57 7. comparators figure 7.1. comparator functi onal block diagram ...... ................................. ........... 60 figure 7.2. comparator hysteres is plot ........... ............................................. ........... 61 8. voltage regulator (reg0) figure 8.1. reg0 configuratio n: usb bus-powered ... ................................. ........... 70 figure 8.2. reg0 configuratio n: usb self-powered ............ ............... ........... ......... 70 figure 8.3. reg0 configurat ion: usb self-powered, regulat or disabled............... 71 figure 8.4. reg0 configuratio n: no usb connection .. ................................ ........... 71 9. cip-51 microcontroller figure 9.1. cip-51 block diagram.. ............................................................... ........... 73 figure 9.2. on-chip memory m ap for 64 kb devices. ................................. ............. 79 figure 9.3. on-chip memory m ap for 32 kb devices. ................................. ............. 80 11. reset sources figure 11.1. reset sources......... .................................................................. ......... 100 figure 11.2. power-on and v dd monitor reset timing .......... ............ .................. 101
rev. 1.3 9 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 12. flash memory figure 12.1. flash program me mory map and security byte... ............ .................. 110 13. external data memory interface and on-chip xram figure 13.1. usb fifo s pace and xram memory map ? with usbfae set to ?1? . ................. ........................................................... ......... 115 figure 13.2. multiplexed confi guration example........ ................................. ........... 119 figure 13.3. non-multiplexed c onfiguration example .............. ............ .................. 120 figure 13.4. emif operat ing modes ............ ................................................. ......... 120 figure 13.5. non-multiplexed 16- bit movx timing ...... ................................. ......... 124 figure 13.6. non-multiplexed 8-bit movx without bank sele ct timing ................. 125 figure 13.7. non-multiplexed 8- bit movx with bank select timing ........... ........... 126 figure 13.8. multiplexed 16-bit movx timing............ ................................. ........... 127 figure 13.9. multiplexed 8-bit movx without bank select ti ming .............. ........... 128 figure 13.10. multiplex ed 8-bit movx with bank select timing .............. .............. 129 14. oscillators figure 14.1. oscillator diagram... .................................................................. ......... 131 15. port input/output figure 15.1. port i/o functi onal block diagram (p ort 0 through port 3) ................ 142 figure 15.2. port i/o cell block diagram ............ .......................................... ......... 143 figure 15.3. peripheral availabi lity on port i/o pins .............. ............... .................. 144 figure 15.4. crossbar priority decoder in example configuration ? (no pins skipped) ........... ......................................................................... ......... 145 figure 15.5. crossbar priority decoder in ? example configuration (3 pins skipped) ........... .............. ............... .................. 146 16. universal serial bus controller (usb0) figure 16.1. usb0 block diagram .. ............................................................... ......... 159 figure 16.2. usb0 register a ccess scheme............... ................................. ......... 162 figure 16.3. usb fifo allocation ................................................................. ......... 167 17. smbus figure 17.1. smbus block diagram .. ............... ............................................. ......... 188 figure 17.2. typical smbus configuration .......... .......................................... ......... 189 figure 17.3. smbus transaction .... ............................................................... ......... 190 figure 17.4. typical smbus scl generation......................................................... 193 figure 17.5. typical master tr ansmitter sequence...... ................................. ......... 199 figure 17.6. typical ma ster receiver sequence................. ................................... 200 figure 17.7. typical slave rece iver sequence............ ................................. ......... 201 figure 17.8. typical slave trans mitter sequence........ ................................. ......... 202 18. uart0 figure 18.1. uart0 block diagram ............. ................................................. ......... 205 figure 18.2. uart0 baud rate logi c ........................................................... ......... 206 figure 18.3. uart interconnect di agram ............. ................................................. 207 figure 18.4. 8-bit uart timing diagram...................................................... ......... 207 figure 18.5. 9-bit uart timing diagram...................................................... ......... 208 figure 18.6. uart multi-proc essor mode interconne ct diagram .......... ................ 209 19. uart1 (c8051f340/1/ 4/5/8/a/b/c only)
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 10 rev. 1.3 figure 19.1. uart1 block diagram ............. ................................................. ......... 213 figure 19.2. uart1 timing without parity or extra bit..... ............................ ......... 215 figure 19.3. uart1 timing with parity ........................................................ ......... 215 figure 19.4. uart1 timing with extra bit .............. .............. ............... .................. 215 figure 19.5. typical uart inte rconnect diagram.................... ............ .................. 216 figure 19.6. uart multi-proc essor mode interconne ct diagram .......... ................ 218 20. enhanced serial pe ripheral interface (spi0) figure 20.1. spi block di agram .............. ............................................................... 222 figure 20.2. multiple-master mode connection diagram .............................. ......... 225 figure 20.3. 3-wire single master and sl ave mode connection di agram ............. 225 figure 20.4. 4-wire single master mode and slav e mode connection diagram ... 225 figure 20.5. master mode data/ clock timing .............. ................................. ......... 227 figure 20.6. slave mode data/clock timing (ckpha = 0) ... ............... .................. 228 figure 20.7. slave mode data/clock timing (ckpha = 1) ... ............... .................. 228 figure 20.8. spi master timing (ckpha = 0)..... .......................................... ......... 232 figure 20.9. spi master timing (ckpha = 1)..... .......................................... ......... 232 figure 20.10. spi slave timing (c kpha = 0).............. ................................. ......... 233 figure 20.11. spi slave timing (c kpha = 1).............. ................................. ......... 233 21. timers figure 21.1. t0 mode 0 bl ock diagram............... .......................................... ......... 236 figure 21.2. t0 mode 2 bl ock diagram............... .......................................... ......... 237 figure 21.3. t0 mode 3 bl ock diagram ............... .......................................... ......... 238 figure 21.4. timer 2 16-bit mode block diagram ........ ................................. ......... 243 figure 21.5. timer 2 8-bit mode block diagram ................... ............... .................. 244 figure 21.6. timer 2 ca pture mode (t2split = ?0?) ......... ............................ ......... 245 figure 21.7. timer 2 ca pture mode (t2split = ?1?) ......... ............................ ......... 246 figure 21.8. timer 3 16-bit mode block diagram ........ ................................. ......... 249 figure 21.9. timer 3 8-bit mode block diagram ................... ............... .................. 250 figure 21.10. timer 3 c apture mode (t3split = ?0?) .............. ............ .................. 251 figure 21.11. timer 3 c apture mode (t3split = ?1?) .............. ............ .................. 252 22. programmable c ounter array (pca0) figure 22.1. pca block diagram.... ............................................................... ......... 255 figure 22.2. pca counter/timer block diagram.......... ................................. ......... 256 figure 22.3. pca interrupt blo ck diagram ................. ................................. ........... 257 figure 22.4. pca capture mode dia gram............. ................................................. 258 figure 22.5. pca software time r mode diagram ........ ................................. ......... 259 figure 22.6. pca high speed out put mode diagram....... ............................ ......... 260 figure 22.7. pca frequen cy output mode ........... ................................................. 261 figure 22.8. pca 8-bit pwm mode diagram ................................................ ......... 262 figure 22.9. pca 16-bit pwm mode ............................................................. ......... 263 figure 22.10. pca module 4 with watchdog ti mer enabled ..... ................. ........... 264 23. c2 interface figure 23.1. typical c2 pin shar ing ............. ................................................. ......... 273
rev. 1.3 11 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d list of tables 1. system overview table 1.1. product select ion guide ................. ............................................. ........... 18 2. absolute maximum ratings table 2.1. absolute maximum rati ngs* ............. .......................................... ........... 24 3. global dc electri cal characteristics table 3.1. global dc electrical characteristics ........... ................................. ........... 25 table 3.2. index to electrical characteristics tables .................... ................ ........... 27 4. pinout and p ackage definitions table 4.1. pin definitions fo r the c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d ................. 28 table 4.2. tqfp-48 package dime nsions ................ ................................. ............. 32 table 4.3. tqfp-48 pcb land pattern dimensions ............ ............... ........... ......... 33 table 4.4. lqfp-32 package dime nsions ................ ................................. ............. 35 table 4.5. lqfp-32 pcb land pattern dimensions ............ ............... ........... ......... 36 5. 10-bit adc (adc 0, c8051f340/1/2/3/ 4/5/6/7/a/b only) table 5.1. adc0 elec trical characteristics .... ............................................... ........... 56 6. voltage reference (c8051f3 40/1/2/3/4/5/6/7/a/b only) table 6.1. voltage reference elec trical characteristi cs .............. ................ ........... 58 7. comparators table 7.1. comparator electrical characteristics ... .............. ............... ........... ......... 68 8. voltage regulator (reg0) table 8.1. voltage regula tor electrical s pecifications ................. ................ ........... 69 9. cip-51 microcontroller table 9.1. cip-51 instruction se t summary .............. ................................. ............. 75 table 9.2. special function regi ster (sfr) memory map ...... ............ ........... ......... 82 table 9.3. special functi on registers ................ .......................................... ........... 83 table 9.4. interrupt summ ary ................. ........................................................ ......... 90 11. reset sources table 11.1. reset electrical char acter istics ........... .............. ............... .................. 106 12. flash memory table 12.1. flash electric al characteristics ....... .......................................... ......... 109 13. external data memory interface and on-chip xram table 13.1. ac parameters for external memory interface ..... ............ .................. 130 14. oscillators table 14.1. oscillator el ectrical characteristics ............ ............................... ......... 141 15. port input/output table 15.1. port i/o dc electrical characteristics ............ ............................ ......... 158 16. universal serial bus controller (usb0) table 16.1. endpoint addr essing scheme ............. .............. ............... .................. 160 table 16.2. usb0 c ontroller registers ......... ............................................... ......... 165 table 16.3. fifo configur ations .............. .................................................. ........... 168 table 16.4. usb transceiver elec trical characteristics .......... ............ .................. 187 17. smbus table 17.1. smbus clock source selection .............. ................................. ........... 192
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 12 rev. 1.3 table 17.2. minimum sda setup and hold times ...... ................................. ......... 193 table 17.3. sources for hardwa re changes to smb0cn ......... ................. ........... 197 table 17.4. smbus status decoding ............... ............................................. ......... 203 18. uart0 table 18.1. timer settings for standard baud rates ? using the internal osci llator ............ .......................................... ......... 212 19. uart1 (c8051f340/1/ 4/5/8/a/b/c only) table 19.1. baud rate generator settings for st andard baud rates ................... 214 20. enhanced serial pe ripheral interface (spi0) table 20.1. spi slave timing para meters ......... .......................................... ......... 234 22. programmable c ounter array (pca0) table 22.1. pca timebase input op tions ............ ................................................. 256 table 22.2. pca0cpm register settings for pca captur e/compare modules .... 257 table 22.3. watchdog timer timeout intervals1 ......... ................................. ......... 265
rev. 1.3 13 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d list of registers sfr definition 5.1. amx0p: amux0 positive channel select . . . . . . . . . . . . . . . . . . . 48 sfr definition 5.2. amx0n: amux 0 negative channel select . . . . . . . . . . . . . . . . . . 49 sfr definition 5.3. adc0cf: adc0 c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 sfr definition 5.4. adc0h: adc0 data word msb . . . . . . . . . . . . . . . . . . . . . . . . . . 50 sfr definition 5.5. adc0l: adc0 data word lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 sfr definition 5.6. adc0cn: adc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 sfr definition 5.7. adc0gth: a dc0 greater-than data high byte . . . . . . . . . . . . . 52 sfr definition 5.8. adc0gtl: ad c0 greater-than data low byte . . . . . . . . . . . . . . 52 sfr definition 5.9. adc0lth: ad c0 less-than data high byte . . . . . . . . . . . . . . . . 53 sfr definition 5.10. adc0ltl: adc0 less-than data low byte . . . . . . . . . . . . . . . 53 sfr definition 6.1. ref0cn: reference control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 sfr definition 7.1. cpt0cn : comparator0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 sfr definition 7.2. cpt0mx : comparator0 mux select ion . . . . . . . . . . . . . . . . . . . . 63 sfr definition 7.3. cpt0md : comparator0 mode selection . . . . . . . . . . . . . . . . . . . . 64 sfr definition 7.4. cpt1cn : comparator1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 sfr definition 7.5. cpt1mx : comparator1 mux select ion . . . . . . . . . . . . . . . . . . . . 66 sfr definition 7.6. cpt1md : comparator1 mode selection . . . . . . . . . . . . . . . . . . . . 67 sfr definition 8.1. reg0cn : voltage regulator control . . . . . . . . . . . . . . . . . . . . . . 72 sfr definition 9.1. dpl: da ta pointer low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 sfr definition 9.2. dph: data pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 sfr definition 9.3. sp: stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 sfr definition 9.4. psw: pr ogram status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 sfr definition 9.5. acc: accu mulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 sfr definition 9.6. b: b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 sfr definition 9.7. ie: interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 sfr definition 9.8. ip: interr upt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 sfr definition 9.9. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 93 sfr definition 9.10. eip1: extended inte rrupt priority 1 . . . . . . . . . . . . . . . . . . . . . . . 94 sfr definition 9.11. eie2: extended interrupt enable 2 . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 9.12. eip2: extended inte rrupt priority 2 . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 9.13. it01cf: int0/int 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . 96 sfr definition 9.14. pc on: power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 sfr definition 10.1. pfe0cn: prefet ch engine control . . . . . . . . . . . . . . . . . . . . . . . 99 sfr definition 11.1. vdm0cn: v dd monitor control . . . . . . . . . . . . . . . . . . . . . . . . . 102 sfr definition 11.2. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 sfr definition 12.1. psctl: program store r/w control . . . . . . . . . . . . . . . . . . . . . 112 sfr definition 12.2. flkey: flash lock and key . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 sfr definition 12.3. flscl: flash scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 sfr definition 13.1. emi0 cn: external memory interface cont rol . . . . . . . . . . . . . . 117 sfr definition 13.2. emi0cf: exter nal memory configuration . . . . . . . . . . . . . . . . . 118 sfr definition 13.3. emi0 tc: external memory timing control . . . . . . . . . . . . . . . . 123 sfr definition 14.1. oscicn: inter nal h-f oscillator control . . . . . . . . . . . . . . . . . . 132 sfr definition 14.2. oscicl: intern al h-f oscillator calibration . . . . . . . . . . . . . . . 133
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 14 rev. 1.3 sfr definition 14.3. osclcn: inter nal l-f oscillator control . . . . . . . . . . . . . . . . . . 134 sfr definition 14.4. oscxcn: external oscillator c ontrol . . . . . . . . . . . . . . . . . . . . 137 sfr definition 14.5. clkmul : clock multiplier control . . . . . . . . . . . . . . . . . . . . . . . 138 sfr definition 14.6. clksel: clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 sfr definition 15.1. xbr0: port i/o crossbar regist er 0 . . . . . . . . . . . . . . . . . . . . . 148 sfr definition 15.2. xbr1: port i/o crossbar regist er 1 . . . . . . . . . . . . . . . . . . . . . 149 sfr definition 15.3. xbr2: port i/o crossbar regist er 2 . . . . . . . . . . . . . . . . . . . . . 149 sfr definition 15.4. p0: port0 latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 15.5. p0mdin : port0 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 15.6. p0mdout: port 0 output mode . . . . . . . . . . . . . . . . . . . . . . . . 151 sfr definition 15.7. p0ski p: port0 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 sfr definition 15.8. p1: port1 latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 sfr definition 15.9. p1mdin : port1 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 sfr definition 15.10. p1mdout: port 1 output mode . . . . . . . . . . . . . . . . . . . . . . . . 152 sfr definition 15.11. p1 skip: port1 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 sfr definition 15.12. p2: port2 latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 sfr definition 15.13. p2mdin : port2 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 sfr definition 15.14. p2mdout: port 2 output mode . . . . . . . . . . . . . . . . . . . . . . . . 154 sfr definition 15.15. p2 skip: port2 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 sfr definition 15.16. p3: port3 latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 sfr definition 15.17. p3mdin : port3 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 sfr definition 15.18. p3mdout: port 3 output mode . . . . . . . . . . . . . . . . . . . . . . . . 155 sfr definition 15.19. p3 skip: port3 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 sfr definition 15.20. p4: port4 latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 sfr definition 15.21. p4mdin : port4 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 sfr definition 15.22. p4mdout: port 4 output mode . . . . . . . . . . . . . . . . . . . . . . . . 157 sfr definition 16.1. usb0x cn: usb0 transceiver control . . . . . . . . . . . . . . . . . . . 161 sfr definition 16.2. usb0a dr: usb0 indirect addre ss . . . . . . . . . . . . . . . . . . . . . . 163 sfr definition 16.3. usb0dat: usb0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 usb register definition 16. 4. index: usb0 endpoint index . . . . . . . . . . . . . . . . . . . 165 usb register definition 16.5. clkrec: clock reco very control . . . . . . . . . . . . . . . 166 usb register definition 16.6. fifon: usb0 endpoint fifo a ccess . . . . . . . . . . . . . 168 usb register definition 16.7. faddr: usb0 function address . . . . . . . . . . . . . . . . 169 usb register definition 16. 8. power: usb0 power . . . . . . . . . . . . . . . . . . . . . . . . 171 usb register definition 16.9. framel: usb0 frame number low . . . . . . . . . . . . . 172 usb register definiti on 16.10. frameh: usb0 frame number high . . . . . . . . . . . 172 usb register definition 16.11. in1int: usb0 in endpoint interrupt . . . . . . . . . . . . . 173 usb register definition 16.12. out1int: usb0 ou t endpoint interrupt . . . . . . . . . . 173 usb register definition 16.13. cmint: usb0 common interrupt . . . . . . . . . . . . . . . 174 usb register definition 16.14. in1ie: usb0 in endpoint interrupt enab le . . . . . . . . 175 usb register definiti on 16.15. out1ie: usb0 out endpoint interrupt enable . . . . . 175 usb register definition 16.16. cmie: usb0 comm on interrupt enable . . . . . . . . . . 176 usb register definition 16.17. e0csr: usb0 endpoi nt0 control . . . . . . . . . . . . . . . 179 usb register definition 16.18. e0cnt: usb0 endpoint 0 data count . . . . . . . . . . . 180
rev. 1.3 15 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d usb register definiti on 16.19. eincsrl: usb0 in endpoi nt control low byte . . . . 182 usb register definiti on 16.20. eincsrh: usb0 in endpoi nt control high byte . . . 183 usb register definition 16. 21. eoutcsrl: usb0 out ? endpoint control low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 usb register definition 16. 22. eoutcsrh: usb0 out ? endpoint control high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 usb register definiti on 16.23. eoutcntl: usb0 out e ndpoint count low . . . . . 186 usb register defini tion 16.24. eoutcnth: usb0 out endpoint count high . . . . 186 sfr definition 17.1. smb0cf: smbus clock/configuration . . . . . . . . . . . . . . . . . . . 194 sfr definition 17.2. smb0cn : smbus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 sfr definition 17.3. smb0dat: smbus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 sfr definition 18.1. scon0: serial port 0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 210 sfr definition 18.2. sbuf0: serial (uart0) port data buffer . . . . . . . . . . . . . . . . . 211 sfr definition 19.1. scon1: uart1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 sfr definition 19.2. smod1: uart1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 sfr definition 19.3. sbuf1: uart1 data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 sfr definition 19.4. sbcon1: ua rt1 baud rate generator cont rol . . . . . . . . . . . 220 sfr definition 19.5. sbrlh1: uart1 baud rate generator high byte . . . . . . . . . . 221 sfr definition 19.6. sbrll1: ua rt1 baud rate generator low by te . . . . . . . . . . . 221 sfr definition 20.1. spi0cfg: spi0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 229 sfr definition 20.2. spi0cn: spi0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 sfr definition 20.3. spi0ck r: spi0 clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 sfr definition 20.4. spi0dat: spi0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 sfr definition 21.1. tcon: timer cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 sfr definition 21.2. tmod: ti mer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 sfr definition 21.3. ckcon: clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 sfr definition 21.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 sfr definition 21.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 sfr definition 21.6. th0: timer 0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 sfr definition 21.7. th1: timer 1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 sfr definition 21.8. tmr2cn: timer 2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 sfr definition 21.9. tmr2rll: ti mer 2 reload register low byte . . . . . . . . . . . . . 248 sfr definition 21.10. tmr2 rlh: timer 2 reload re gister high byte . . . . . . . . . . . 248 sfr definition 21.11. tmr2l: timer 2 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 sfr definition 21.12. tmr2h timer 2 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 sfr definition 21.13. tmr3cn: timer 3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 sfr definition 21.14. tmr3 rll: timer 3 reload regi ster low byte . . . . . . . . . . . . 254 sfr definition 21.15. tmr3 rlh: timer 3 reload re gister high byte . . . . . . . . . . . 254 sfr definition 21.16. tmr3l: timer 3 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 sfr definition 21.17. tmr3h timer 3 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 sfr definition 22.1. pca0cn: pca control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 sfr definition 22.2. pca0md: pca mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 sfr definition 22.3. pc a0cpmn: pca capture/compare mode . . . . . . . . . . . . . . . 268 sfr definition 22.4. pca0l: pca counter/timer low byte . . . . . . . . . . . . . . . . . . . 269 sfr definition 22.5. pca0h: pca counter/timer high byte . . . . . . . . . . . . . . . . . . . 269
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 16 rev. 1.3 sfr definition 22.6. pca0cpln: pca capture module low byte . . . . . . . . . . . . . . . 269 sfr definition 22.7. pca0cphn: pca capture module high byte . . . . . . . . . . . . . . 270 c2 register definition 23.1. c2add: c2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 c2 register definition 23.2. device id: c2 device id . . . . . . . . . . . . . . . . . . . . . . . . 271 c2 register definition 23.3. revid: c2 revision id . . . . . . . . . . . . . . . . . . . . . . . . . 272 c2 register definition 23.4. fp ctl: c2 flash programming cont rol . . . . . . . . . . . . 272 c2 register definition 23.5. fp dat: c2 flash programming data . . . . . . . . . . . . . . 272
rev. 1.3 17 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 1. system overview c8051f340/1/2/3/4/5/6/7 /8/9/a/b/c/d devices are fully integrated mixed-signal system-on-a-chip mcus. highlighted features are listed below. refer to table 1.1 for specific product feature selection. ? high-speed pipelined 8051-compatible microcontroller core (up to 48 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? universal serial bus (usb) function controller wit h eigh t flexible endpoint pipes, integrated trans - ceiver, and 1 kb fifo ram ? supply voltage regulator ? true 10-bit 200 ksps differential / single-ended ad c with analog multiplexer ? on-chip voltage reference and temperature sensor ? on-chip voltage comparators (2) ? precision internal calibrated 12 mhz internal oscillator and 4x clock multiplier ? internal low-frequency oscillato r for additional pow er savings ? up to 64 kb of on-chip flash memory ? up to 4352 bytes of on-chip ram (256 + 4 kb) ? external memory interface (emif) available on 48-pin versions. ? smbus/i2c, up to 2 uarts, and enhanced spi ser ial interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with five capture/compare modules and watchdog timer func tion ? on-chip power-on reset, v dd monitor, and missing clock detector ? up to 40 port i/o (5 v tolerant) with on-chip powe r-on reset, v dd monitor, voltage regulator, watc hdog timer, and clock oscillator, c8051f340/1/2/3/4/5/6 /7/8/9/a/b/c/d devices are truly stand- alone system-on-a-chip solutions. the flash memory can be reprogrammed in-circuit, providin g non-volatile data storage, and also allowing field upgrades of the 8051 firmware. user software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. the on-chip silicon labs 2- wire (c2) d evelopment interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions , allowing in-system debugging with - out occupying package pins. each device is specified for 2.7?5.25 v operation over the industrial temperature range (?40 to +85 c). f or voltages above 3.6 v, the on-chip voltage regulator must be used. a minimum of 3.0 v is required for usb com munication. the port i/o and rst pins are tolerant of input signals up to 5 v. c8051f340/1/2/3/ 4/ 5/6/7/8/9/a/b/c/d devices are available in 48-pin tqfp, 32-pin lqfp, or 32-pin qfn packages. see ta b l e 1.1, ?product selection guide,? on page 18 for feature and package choices.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 18 rev. 1.3 table 1.1. product selection guide ordering part number mips (peak) flash memory (bytes) ram calibrated internal oscillator low frequency oscillator usb with 1k endpoint ram supply voltage regulator smbus/i2c enhanced spi uarts timers (16-bit) programmable counter array digital port i/os external memory interface (emif) 10-bit 200 ksps adc temperature sensor voltage reference analog comparators package c8051f340-gq 48 64k 4352 ?????? 24 ? 40 ???? 2tqfp48 C8051F341-GQ 48 32k 2304 ?????? 24 ? 40 ???? 2tqfp48 c8051f342-gq 48 64k 4352 ?????? 14 ? 25 ? ??? 2lqfp32 c8051f342-gm 48 64k 4352 ?????? 14 ? 25 ? ??? 2qfn32 c8051f343-gq 48 32k 2304 ?????? 14 ? 25 ? ??? 2lqfp32 c8051f343-gm 48 32k 2304 ?????? 14 ? 25 ? ??? 2qfn32 c8051f344-gq 25 64k 4352 ?????? 24 ? 40 ???? 2tqfp48 c8051f345-gq 25 32k 2304 ?????? 24 ? 40 ???? 2tqfp48 c8051f346-gq 25 64k 4352 ? ? ???? 14 ? 25 ? ??? 2lqfp32 c8051f346-gm 25 64k 4352 ? ? ???? 14 ? 25 ? ??? 2qfn32 c8051f347-gq 25 32k 2304 ? ? ???? 14 ? 25 ? ??? 2lqfp32 c8051f347-gm 25 32k 2304 ? ? ???? 14 ? 25 ? ??? 2qfn32 c8051f348-gq 25 32k 2304 ?????? 24 ? 40 ? ? ? ? 2 tqfp48 c8051f349-gq 25 32k 2304 ?????? 14 ? 25 ? ? ? ? 2 lqfp32 c8051f349-gm 25 32k 2304 ?????? 14 ? 25 ???? 2 qfn32 c8051f34a-gq 48 64k 4352 ?????? 24 ? 25 ? ??? 2lqfp32 c8051f34a-gm 48 64k 4352 ?????? 24 ? 25 ? ??? 2qfn32 c8051f34b-gq 48 32k 2304 ?????? 24 ? 25 ? ??? 2lqfp32 c8051f34b-gm 48 32k 2304 ?????? 24 ? 25 ? ??? 2qfn32 c8051f34c-gq 48 64k 4352 ?????? 24 ? 40 ? ? ? ? 2 tqfp48 c8051f34d-gq 48 64k 4352 ?????? 14 ? 25 ? ? ? ? 2 lqfp32
rev. 1.3 19 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 1.1. c8051f340/1/4/5 block diagram analog peripherals 10-bit 200ksps adc a m u x temp sensor 2 comparators + - vref vdd cp0 vdd + - cp1 vref debug / programming hardware port 0 drivers p0.0 ain0 - ain19 port i/o configuration digital peripherals priority crossbar decoder crossbar control power-on reset power net uart0 timers 0, 1, 2, 3 pca/wdt smbus uart1 spi p0.1 p0.2 p0.3 p0.4 p0.5 p0.6/xtal1 p0.7/xtal2 port 1 drivers port 2 drivers port 3 drivers port 4 drivers p1.0 p1.1 p1.2 p1.3 p1.4/cnvstr p1.5/vref p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 supply monitor system clock setup external oscillator internal oscillator xtal1 xtal2 low freq. oscillator clock multiplier clock recovery usb peripheral controller 1k byte ram full / low speed transceiver external memory interface control address data p1 p2 / p3 p4 sfr bus voltage regulator d+ d- vbus vdd vreg gnd c2ck/rst reset c2d cip-51 8051 controller core 64/32k byte isp flash program memory 256 byte ram 4/2k byte xram
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 20 rev. 1.3 figure 1.2. c8051f342/3/6/7 block diagram analog peripherals 10-bit 200 ksps adc a m u x temp sensor 2 comparators + - vref vdd cp0 vdd + - cp1 vref debug / programming hardware port 0 drivers p0.0 ain0 - ain20 port i/o configuration digital peripherals priority crossbar decoder crossbar control power-on reset power net uart0 timers 0, 1, 2, 3 pca/wdt smbus spi p0.1 p0.2/xtal1 p0.3/xtal2 p0.4 p0.5 p0.6/cnvstr p0.7/vref port 1 drivers port 2 drivers port 3 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0/c2d supply monitor system clock setup external oscillator internal oscillator xtal1 xtal2 low freq. oscillator* clock multiplier clock recovery usb peripheral controller 1 kb ram full / low speed transceiver sfr bus voltage regulator d+ d- vbus vdd vreg gnd c2ck/rst reset cip-51 8051 controller core 64/32 kb isp flash program memory 256 byte ram 4/2 kb xram c2d *low frequency oscillator option not available on c8051f346/7
rev. 1.3 21 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 1.3. c8051f348/c block diagram debug / programming hardware port 0 drivers p0.0 port i/o configuration digital peripherals priority crossbar decoder crossbar control power-on reset power net uart0 timers 0, 1, 2, 3 pca/wdt smbus uart1 spi p0.1 p0.2 p0.3 p0.4 p0.5 p0.6/xtal1 p0.7/xtal2 port 1 drivers port 2 drivers port 3 drivers port 4 drivers p1.0 p1.1 p1.2 p1.3 p1.4/cnvstr p1.5/vref p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 supply monitor system clock setup external oscillator internal oscillator xtal1 xtal2 low freq. oscillator clock multiplier clock recovery usb peripheral controller 1k byte ram full / low speed transceiver external memory interface control address data p1 p2 / p3 p4 voltage regulator d+ d- vbus vdd vreg gnd c2ck/rst reset c2d cip-51 8051 controller core 64/32 kb isp flash program memory 256 byte ram 4/2 kb xram analog peripherals 2 comparators + - cp0 + - cp1 sfr bus
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 22 rev. 1.3 figure 1.4. c8051f349/d block diagram debug / programming hardware port 0 drivers p0.0 port i/o configuration digital peripherals priority crossbar decoder crossbar control power-on reset power net uart0 timers 0, 1, 2, 3 pca/wdt smbus spi p0.1 p0.2/xtal1 p0.3/xtal2 p0.4 p0.5 p0.6/cnvstr p0.7/vref port 1 drivers port 2 drivers port 3 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0/c2d supply monitor system clock setup external oscillator internal oscillator xtal1 xtal2 low freq. oscillator clock multiplier clock recovery usb peripheral controller 1 kb ram full / low speed transceiver sfr bus voltage regulator d+ d- vbus vdd vreg gnd c2ck/rst reset cip-51 8051 controller core 64/32 kb isp flash program memory 256 byte ram 4/2 kb xram c2d analog peripherals 2 comparators + - cp0 + - cp1
rev. 1.3 23 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 1.5. c8051f34a/b block diagram analog peripherals 10-bit 200 ksps adc a m u x temp sensor 2 comparators + - vref vdd cp0 vdd + - cp1 vref debug / programming hardware port 0 drivers p0.0 ain0 - ain20 port i/o configuration digital peripherals priority crossbar decoder crossbar control power-on reset power net uart0 timers 0, 1, 2, 3 pca/wdt smbus spi p0.1 p0.2/xtal1 p0.3/xtal2 p0.4 p0.5 p0.6/cnvstr p0.7/vref port 1 drivers port 2 drivers port 3 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0/c2d supply monitor system clock setup external oscillator internal oscillator xtal1 xtal2 low freq. oscillator* clock multiplier clock recovery usb peripheral controller 1 kb ram full / low speed transceiver sfr bus voltage regulator d+ d- vbus vdd vreg gnd c2ck/rst reset cip-51 8051 controller core 64/32 kb isp flash program memory 256 byte ram 4/2 kb xram c2d uart1
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 24 rev. 1.3 2. absolute maximum ratings table 2.1. absolute maximum ratings* parameter conditions min typ max units ambient temperature under bias ?55 125 c storage temperature ?65 150 c voltage on any port i/o pin or rst with respect to gnd ?0.3 5.8 v voltage on v dd with respect to gnd ?0.3 4.2 v maximum total current through v dd and gnd 500 ma maximum output current sunk by rst or any port pin 100 ma *note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the devices at thos e or any other conditions above those indicated in the operation listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
rev. 1.3 25 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 3. global dc electrical characteristics table 3.1. global dc electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units digital supply voltage 1 vrst 3.3 3.6 v digital supply ram data retention voltage 1.5 v sysclk (system clock) 2 c8051f340/1/2/3/a/b/c/d c8051f344/5/6/7/8/9 0 0 48 25 mhz specified operating ? temperature range ?40 +85 c digital supply current - cpu active (normal mode, accessing flash) i dd 3 v dd = 3.3 v, sysclk = 48 mhz ? v dd = 3.3 v, sysclk = 24 mhz ? v dd = 3.3 v, sysclk = 1 mhz ? v dd = 3.3 v, sysclk = 80 khz v dd = 3.6 v, sysclk = 48 mhz ? v dd = 3.6 v, sysclk = 24 mhz 25.9 13.9 0.69 55 29.7 15.9 28 .5 15.7 32.3 18 ma ma ma a ma ma i dd supply sensitivity 3,4 sysclk = 1 mhz, ? relative to v dd = 3.3 v sysclk = 24 mhz, ? relative to v dd = 3.3 v 47 46 %/v %/v i dd frequency sensitivity 3,5 v dd = 3.3 v, sysclk < 30 mhz, ? t = 25 oc v dd = 3.3 v, sysclk > 30 mhz, ? t = 25 oc v dd = 3.6 v, sysclk < 30 mhz, ? t = 25 oc v dd = 3.6 v, sysclk > 30 mhz, ? t = 25 oc 0.69 0.44 0.80 0.50 ma/ mhz ma/mhz ma/mhz ma/mhz digital supply current - cpu inacti ve (idle mode, not accessing flash) i dd 3 v dd = 3.3 v, sysclk = 48 mhz ? v dd = 3.3 v, sysclk = 24 mhz ? v dd = 3.3 v, sysclk = 1 mhz ? v dd = 3.3 v, sysclk = 80 khz v dd = 3.6 v, sysclk = 48 mhz ? v dd = 3.6 v, sysclk = 24 mhz 16.6 8.25 0.44 35 18.6 9.26 18 .75 9.34 20.9 10.5 ma ma ma a ma ma i dd supply sensitivity 3,4 sysclk = 1 mhz, ? relative to v dd = 3.3 v sysclk = 24 mhz, ? relative to v dd = 3.3 v 41 39 %/v %/v
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 26 rev. 1.3 other electrical characteristics tables are found in the data sheet section corresponding to the associated peripherals. for more information on electrical characte ristics for a specific perip heral, refer to the page indicated in ta b l e 3.2 . i dd frequency sensitivity 3,6 v dd = 3.3 v, sysclk < 1 mhz, ? t = 25 oc v dd = 3.3 v, sysclk > 1 mhz, ? t = 25 oc v dd = 3.6 v, sysclk < 1 mhz, ? t = 25 oc v dd = 3.6 v, sysclk > 1 mhz, ? t = 25 oc 0.44 0.32 0.49 0.36 ma/ mhz ma/mhz ma/mhz ma/mhz digital supply current (stop mode, shutdown) oscillator no t running, ? v dd monitor disabled < 0.1 a digital supply current for usb module (usb active mode) v dd = 3.3 v, usb clock = 48 mhz v dd = 3.6 v, usb clock = 48 mhz 8.69 9.59 ma ma digital supply current for usb module (usb suspend mode) oscillator no t running ? v dd monitor disabled < 0.1 a notes: 1. usb r equires 3.0 v minimum supply voltage. 2. sysclk mu st be at least 32 khz to enable debugging. 3. based on device characterization of data; not production tested. 4. acti ve and inactive i dd at voltages and frequencies other than thos e specified can be calculated using the i dd supply sensitivity. for example, if the v dd is 3.0 v instead of 3.3 v at 24 mhz: i dd = 13.9 ma typical at 3.3 v and sysclk = 24 mhz. from this, i dd = 13.9 ma + 0.46 x (3 .0 v ? 3.3 v) = 13.76 ma at 3.0 v and sysclk = 24 mhz. 5. i dd can be estimated for frequencies < 30 mhz by multiplying the frequency of interest by the frequency sensitivity number for that range. w hen using these numbers to estimate i dd for > 30 mhz, the estimate should be the current at 24 mhz (or 48 mhz) minus the differ ence in current indicated by the frequency sensitivity number. for example: v dd = 3.3 v; sysclk = 35 mhz, i dd = 13.9 ma ? (24 mhz ? 35 mhz) x 0.44 ma/mhz = 18.74 ma. 6. id le i dd can be estimated for frequencies < 1 mhz by multiplying the frequency of interest by the frequency sensitivity number for that range. when using these numbers to estimate idle i dd for > 1 mhz, the estimate should be the current at 24 mhz (or 48 mhz) minus th e difference in current indicated by the frequency sensitivity number. for example: v dd = 3.3 v; sysclk = 5 mhz, idle i dd = 8.25 ma ? (24 mhz ? 5 mhz) x 0.32 ma/mhz = 2.17 ma. table 3.1. global dc electrical characte ristics (continued) ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units
rev. 1.3 27 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d table 3.2. index to electrical characteristics tables table title page no. adc0 electrical characteristics 56 voltage reference electr ical char acteristics 58 comparator electrical characteristics 68 voltage regulator electrical specifications 69 reset electrical characteristics 106 flash electrical ch aracteristics 109 ac parameters for exte r nal memory interface 130 oscillator electrical characteristics 141 port i/o dc electrical characteristics 158 usb transceiver electrical characteristics 187
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 28 rev. 1.3 4. pinout and package definitions table 4.1. pin definitions for the c8051f 340/1/2/3/4/5/6/7/8/9/a/b/c/d name pin numbers type description 48-pin 32-pin v dd 10 6 power in power out 2.7?3.6 v power supply voltage input. 3.3 v voltage regulator output. see section 8 . gnd 7 3 ground. rst / c2ck 13 9 d i/o d i/o device reset. open-drain output of internal por or v dd monitor. an external source can initiate a system reset by driving this pin low for at least 15 s. see section 11 . clock signal for the c2 debug interface. c2d 14 ? d i/o bi-directional data signal for the c2 debug interface. p3.0 / c2d ? 10 d i/o d i/o port 3.0. see section 15 for a complete description of port 3. bi-directional data signal for the c2 debug interface. regin 11 7 power in 5 v regulator input. this pin is the input to the on-chip volt - age regulator. vbus 12 8 d in vbus sense input. this pin should be connected to the vbus signal of a usb network. a 5 v signal on this pin indi - cates a usb network connection. d+ 8 4 d i/o usb d+. d- 9 5 d i/o usb d?. p0.0 6 2 d i/o or a in port 0.0. see section 15 for a complete description of port 0. p0.1 5 1 d i/o or a in port 0.1. p0.2 4 32 d i/o or a in port 0.2. p0.3 3 31 d i/o or a in port 0.3. p0.4 2 30 d i/o or a in port 0.4. p0.5 1 29 d i/o or a in port 0.5. p0.6 48 28 d i/o or a in port 0.6. p0.7 47 27 d i/o or a in port 0.7.
rev. 1.3 29 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d p1.0 46 26 d i/o or a in port 1.0. see section 15 for a complete description of port 1. p1.1 45 25 d i/o or a in port 1.1. p1.2 44 24 d i/o or a in port 1.2. p1.3 43 23 d i/o or a in port 1.3. p1.4 42 22 d i/o or a in port 1.4. p1.5 41 21 d i/o or a in port 1.5. p1.6 40 20 d i/o or a in port 1.6. p1.7 39 19 d i/o or a in port 1.7. p2.0 38 18 d i/o or a in port 2.0. see section 15 for a complete description of port 2. p2.1 37 17 d i/o or a in port 2.1. p2.2 36 16 d i/o or a in port 2.2. p2.3 35 15 d i/o or a in port 2.3. p2.4 34 14 d i/o or a in port 2.4. p2.5 33 13 d i/o or a in port 2.5. p2.6 32 12 d i/o or a in port 2.6. p2.7 31 11 d i/o or a in port 2.7. p3.0 30 ? d i/o or a in port 3.0. see section 15 for a complete description of port 3. p3.1 29 ? d i/o or a in port 3.1. p3.2 28 ? d i/o or a in port 3.2. table 4.1. pin definitions for the c8051f340/1/2/3/4/5/6/ 7/8/9/a/b/c/d (continued) name pin numbers type description 48-pin 32-pin
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 30 rev. 1.3 p3.3 27 ? d i/o or a in port 3.3. p3.4 26 ? d i/o or a in port 3.4. p3.5 25 ? d i/o or a in port 3.5. p3.6 24 ? d i/o or a in port 3.6. p3.7 23 ? d i/o or a in port 3.7. p4.0 22 ? d i/o or a in port 4.0. see section 15 for a complete description of port 4. p4.1 21 ? d i/o or a in port 4.1. p4.2 20 ? d i/o or a in port 4.2. p4.3 19 ? d i/o or a in port 4.3. p4.4 18 ? d i/o or a in port 4.4. p4.5 17 ? d i/o or a in port 4.5. p4.6 16 ? d i/o or a in port 4.6. p4.7 15 ? d i/o or a in port 4.7. table 4.1. pin definitions for the c8051f340/1/2/3/4/5/6/ 7/8/9/a/b/c/d (continued) name pin numbers type description 48-pin 32-pin
rev. 1.3 31 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 4.1. tqfp-48 pi nout diagram (top view) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 vbus p2.2 p2.0 p1.7 p1.6 p1.2 p2.4 p2.3 p3.5 p3.4 p3.2 p3.1 p2.1 p0.6 p3.3 p0.7 p0.2 d- regin p0.3 p3.0 p1.4 p1.5 p0.5 p1.1 p1.0 p0.4 p1.3 13 14 15 16 17 18 19 20 21 22 23 24 p2.6 p2.5 c8051f340/1/4/5/8/c-gq top view gnd d+ p0.1 p0.0 vdd p2.7 p3.6 p4.1 p4.0 p3.7 p4.2 p4.5 p4.4 p4.3 p4.6 rst / c2ck c2d p4.7
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 32 rev. 1.3 figure 4.2. tqfp-48 package diagram table 4.2. tqfp-48 package dimensions dimension min nom max a??1 . 2 0 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 b 0 . 1 70 . 2 20 . 2 7 c 0.09 ? 0.20 d9 . 0 0 b s c d1 7.00 bsc e0 . 5 0 b s c e9 . 0 0 b s c e1 7.00 bsc l 0 . 4 50 . 6 00 . 7 5 aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 ? 0 3.5 7 notes: 1. all dimen sions shown are in millimeters (mm) unless otherwise noted. 2. dimensi oning and tolerancing per ansi y14.5m-1994. 3. thi s drawing conforms to jedec outline ms-026, variation abc. 4. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
rev. 1.3 33 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 4.3. tqfp-48 recommended pcb land pattern table 4.3. tqfp-48 pcb land pattern dimensions dimension min max c1 8.30 8.40 c 2 8.30 8.40 e 0.50 bsc x1 0.20 0.30 y1 1.40 1.50 notes: general: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. t his land pattern design is based on the ipc-7351 guidelines. solder mask design: 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 4. a st ainless steel, laser-cut and electro- polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. t he stencil thickness should be 0.125 mm (5 mils). 6. t he ratio of stencil aperture to land pad size should be 1:1 for all pads. card assembly: 7. a no-cle an, type-3 solder paste is recommended. 8. t he recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 34 rev. 1.3 figure 4.4. lqfp-32 pi nout diagram (top view) 1 vbus p1.2 p1.7 p1.4 p1.3 p1.5 d+ d- gnd p0.1 p0.0 p2.0 p2.1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p1.6 c8051f342/3/6/7/9/a/b/d-gq top view vdd regin rst / c2ck p3.0 / c2d p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2
rev. 1.3 35 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 4.5. lqfp-32 package diagram table 4.4. lqfp-32 package dimensions dimension min nom max a??1 . 6 0 a1 0.05 ? 0.15 a2 1.35 1.40 1.45 b 0 . 3 00 . 3 70 . 4 5 c 0.09 ? 0.20 d9 . 0 0 b s c d1 7.00 bsc e0 . 8 0 b s c e9 . 0 0 b s c e1 7.00 bsc l 0 . 4 50 . 6 00 . 7 5 aaa 0.20 bbb 0.20 ccc 0.10 ddd 0.20 ? 0 3.5 7 notes: 1. all dimen sions shown are in millimeters (mm) unless otherwise noted. 2. dimensi oning and tolerancing per ansi y14.5m-1994. 3. thi s drawing conforms to jedec outline ms-026, variation bba. 4. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 36 rev. 1.3 figure 4.6. lqfp-32 recommended pcb land pattern table 4.5. lqfp-32 pcb land pattern dimensions dimension min max c1 8.40 8.50 c 2 8.40 8.50 e 0.80 bsc x1 0.40 0.50 y1 1.25 1.35 notes: general: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. t his land pattern design is based on the ipc-7351 guidelines. solder mask design: 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 4. a st ainless steel, laser-cut and electro- polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. t he stencil thickness should be 0.125 mm (5 mils). 6. t he ratio of stencil aperture to land pad size should be 1:1 for all pads. card assembly: 7. a no-cle an, type-3 solder paste is recommended. 8. t he recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
rev. 1.3 37 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 4.7. qfn-32 pino ut diagram (top view) 25 p1.1 17 p2.1 16 p2.2 8 vbus 32 31 30 29 28 27 26 1 2 3 4 5 6 7 9 10 11 12 13 14 15 24 23 22 21 20 19 18 gnd (optional) c8051f342/3/6/7/9/a/b-gm top view p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 gnd d+ d- vdd regin rst / c2ck p3.0 / c2d p2.7 p2.6 p2.5 p2.4 p2.3 p2.0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 38 rev. 1.3 figure 4.8. qfn-32 package drawing table 4.6. qfn-32 package dimensions dimension min nom max a 0.80 0.9 1.00 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 5.00 bsc d2 3.20 3.30 3.40 e 0.50 bsc e 5.00 bsc e2 3.20 3.30 3.40 l 0.30 0.40 0.50 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. di mensioning and tolerancing per ansi y14.5m-1994. 3. t his drawing conforms to the je dec solid state outline mo-220, variation vhhd except for custom features d2, e2, and l which are toleranced per supplier designation. 4. re commended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
rev. 1.3 39 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d l1 0.00 ? 0.15 aaa ? ? 0.15 bb b ? ? 0.10 ddd ? ? 0.05 eee ? ? 0.08 table 4.6. qfn-32 package dimensions (continued) dimension min nom max notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the je dec solid state outline mo-220, variation vhhd except for custom features d2, e2, and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 40 rev. 1.3 figure 4.9. qfn-32 recomm ended pcb land pattern table 4.7. qfn-32 p cb land pattern dimesions dimension min max dimension min max c1 4.80 4.90 x2 3.20 3.40 c2 4.80 4.90 y1 0.75 0.85 e 0.50 bsc y2 3.20 3.40 x1 0.20 0.30 notes: general: 1. al l dimensions shown are in millim eters (mm) unless otherwise noted. 2. t his land pattern design is based on the ipc-7351 guidelines. solder mask design: 3. al l metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design: 4. a st ainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. th e stencil thickness should be 0.125 mm (5 mils). 6. t he ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 7. a 3x3 array of 1.0 mm openings on a 1.2mm pitch should be used for the center pad to assure th e proper paste volume. card assembly: 8. a no-cl ean, type-3 solder paste is recommended. 9. t he recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
rev. 1.3 41 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 5. 10-bit adc (adc0, c8051f340 /1/2/3/4/5/6/7/a/b only) the adc0 subsystem for the c8051f34 x devices consists of two analog multiplexers (ref erred to collec - tively as amux0), and a 200 ksps, 10-bit successive-approximation-register adc with integrated tra ck-and-hold and programmable window detector. the amux0, data conversion modes, and window detector are all configured under software control via the special function registers shown in figure 5.1 . adc0 operates in both single-ended and differential modes, and may be configured to measure voltages a t port pins, the temperature sensor output, or v dd with respect to a port pin, vref, or gnd. the connec - tion options for amux0 are detailed in sfr definition 5.1 and sfr definition 5.2 . the adc0 subsystem is enabled only when the ad0en bit in the adc0 control register (adc0cn ) is set to logic 1. the adc0 sub - system is in low power shutdo wn when this bit is logic 0. figure 5.1. adc0 functional block diagram adc0cf ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic gnd 101 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l amx0p amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 amx0n amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 ain+ ain- vref positive input (ain+) amux vdd negative input (ain-) amux temp sensor port i/o pins* port i/o pins* * 21 selections on 32-pin package 20 selections on 48-pin package
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 42 rev. 1.3 5.1. analog multiplexer amux0 selects the positive and negative inputs to the adc. the positive input (ain+) can be connected to individual port pins, the on-chip temperature sensor, or the positive power supply (v dd ). the negative input (ain-) can be connected to individual port pins, vref, or gnd. when gnd is selected as the neg - ative input, adc0 operates in single-ended mode; at all other times, adc0 operates in differential mo de. the adc0 input channels are selected in the amx0p and amx0n registers as described in sfr definition 5.1 and sfr definition 5.2 . the conversion code format differs between single -en ded and differential modes. the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left -justified, depending on the setting of the ad0ljst bit (adc0cn.0). when in single-ended mode, conversion codes are represented as 10-bit unsigned integers. inputs are measured from ?0? to vref x 1023/1024. example codes are shown below for both right-justi - fied and left-justified data. unused bits in the adc0h and adc0l registers are set to ?0?. when in differential mode, conversion codes are represented as 10-bit signed 2?s complement numbers. inp uts are measured from ?vref to vref x 511/512. example codes are shown below for both right-jus - tified and left-justified data. for right-justified data, the unused msbs of adc0h are a sign-extension of the data word. for left-justified data, the unused lsbs in the adc0l register are set to ?0?. important note about adc0 input configuration: por t pins selected as adc0 inputs should be config - ured as analog inputs, and should be skipped by the dig ital crossbar. to configure a port pin for analog input, set to ?0? the corresponding bit in register pnmd in (for n = 0,1,2,3). to fo rce the crossbar to skip a port pin, set to ?1? the corresponding bit in register pnskip (for n = 0,1,2). see section ?15. port input/ output? on page 142 for more port i/o co nfiguration details. input voltage ( single-ended) right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage (differential) right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 511/512 0x01ff 0x7fc0 vref x 256/512 0x0100 0x4000 0 0x0000 0x0000 ?vref x 256/512 0xff00 0xc000 ?vref 0xfe00 0x8000
rev. 1.3 43 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 5.2. temperature sensor the temperature sensor transfer function is shown in figure 5.2 . the output voltage (v temp ) is the positive adc input when the temperature sensor is selected by bits amx0p4-0 in register amx0p. values for the of fset and slope parameters can be found in ta b l e 5.1 . figure 5.2. temperature sensor transfer function the uncalibrated temperature sensor output is extrem e ly linear and suitable for relative temperature mea - surements (see ta b l e 5.1 for linearity specifications). for absolu te tem perature measurements, offset and/ or gain calibration is recommended. typically a 1-po int (of fset) calibration in cludes the following steps: step 1. control/measure the ambient temper atur e (this temperature must be known). step 2. power the device, and delay for a few seconds to allow for self-heating. step 3. perform an adc conversion with the te mperature sensor selected as the positive input and gnd selected as the negative input. step 4. calculate the offset characteristics, a nd store this value in non-volatile memory for use with subsequent temperatur e sensor measurements. figure 5.3 shows the typical temperature sensor erro r assuming a 1-point calibration at 25 c. note that parameters which affect adc measurement, in particular the voltage reference value, will also a ffect temperature measurement. temperature voltage v temp = ( gain x temp c ) + offset offset (v at 0 celsius) gain (v / deg c) temp c = (v temp - offset ) / gain
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 44 rev. 1.3 figure 5.3. temperature sensor error with 1-point calibration (vref = 2.40 v) -40.00 -20.00 0.0 0 20.0 0 40.0 0 60.0 0 80.0 0 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.0 0 1.0 0 2.0 0 3.0 0 4.0 0 5.0 0 -5.00 -4.00 -3.00 -2.00 -1.00 0.0 0 1.0 0 2.0 0 3.0 0 4.0 0 5.0 0
rev. 1.3 45 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 5.3. modes of operation adc0 has a maximum conversion speed of 200 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register (system clock divided by (ad0sc + 1) for 0 ? ad0sc ? ? 31). 5.3.1. starting a conversion a conversion can be initiated in one of five ways, dep ending on the programmed states of the adc0 start of conversion mode bits (ad0cm2?0) in register adc0 cn. conversions may be initiated by one of the fol - lowing: 1. writing a ?1? to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., timed co ntinuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal 6. a timer 3 overflow writing a ?1? to ad0busy provides software cont ro l of adc0 whereby conversions are performed "on-demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conver - sion is complete. the fallin g edge of a d0busy triggers an interrup t (when enabled) and sets the adc0 interrupt flag (ad0int). note: when polling for adc conversion comple tions, the adc0 interrupt flag (ad0int) should be used. converted data is availa ble in the adc0 data regist ers, adc0h:adc0l, when bit ad0int is logic 1. note that when timer 2 or time r 3 overflows are used as the conversion source, low byte overflows are used if timer 2/3 is in 8-bit mode; high byte overflows are used if timer 2/3 is in 16-bit mode. see section ?21. timers? on page 235 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as a port pin. when the cnvstr input is used as the adc0 conversion source, the associated port pin should be skipped by the digital crossbar. to configure the crossbar to skip a pin, set the corresponding bit in the pnskip register to ?1?. see section ?15. port input/output? on page 142 for details on port i/o configuration.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 46 rev. 1.3 5.3.2. tracking modes the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked, except when a conversi on is in progress. when the ad0tm bit is logic 1, adc0 operates in low-power track-and-hold mode. in this mode, each conversion is preceded by a track - ing period of 3 sar clocks (after the start-of-convers ion s ignal). when the cnvstr signal is used to initi - ate conversions in low-power tracking mode, adc0 tr ac ks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 5.4 ). tracking can also be disabled (shutdown) when the device is in low power standby or sleep mod es. low-power track-and-hold mode is also useful when amux set - tings are frequently changed, due to the settling time requirements described in section ?5.3.3. settling time requirements? on page 47 . figure 5.4. 10-bit adc track and conversion example timing write '1' to ad0busy, timer 0, timer 2, timer 1, timer 3 overflow (ad0cm[2:0]=000, 001,010 011, 101) ad0tm=1 track convert low power mode ad0tm=0 track or convert convert track low power or convert sar clocks 123456789101112 123456789 sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr (ad0cm[2:0]=100) ad0tm=1 a. adc0 timing for external trigger source sar clocks track or convert convert track ad0tm=0 track convert low power mode low power or convert 10 11 13 14 10 11
rev. 1.3 47 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 5.3.3. settling time requirements when the adc0 input configuration is changed (i.e., a different amux0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. this tracking time is determined by the amux0 resistance, the adc0 sampling capacita nce, any external source resistance, and the accu - racy required for the conversion. note that in low-po we r tracking mode, three sar clocks are used for tracking at the start of every conv ersion. for most applications, these three sar clocks will meet the mini - mum tracking time requirements. figure 5.5 shows the equivalent adc0 input circuits for b oth differential and single-ended modes. notice that the equivalent time constant for both input circ uit s is the same. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 5.1 . when measuring the temperature sensor output or v dd with respect to gnd, r total reduces to r mux . see ta b l e 5.1 for adc0 minimum settling time requirements. equation 5.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the ad c resolution in bits (10). figure 5.5. adc0 eq uivalent input circuits t 2 n sa ------ - ?? ?? r total c sample ? mux select mux select differential mode px.x px.x r mux = 5k c sample = 5pf rc input = r mux * c sample mux select single-ended mode px.x
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 48 rev. 1.3 sfr definition 5.1. amx0p: amux0 positive channel select bits7?5: unused. read = 000b; write = don?t care. bits4?0: amx0p4?0: amux0 positive input selection r r r r/w r/w r/w r/w r/w reset value - - - amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbb amx0p4-0 adc0 positive input (32-pin package) adc0 positive input (48-pin package) 00000 p1.0 p2.0 00001 p1.1 p2.1 00010 p1.2 p2.2 00011 p1.3 p2.3 00100 p1.4 p2.5 00101 p1.5 p2.6 00110 p1.6 p3.0 00111 p1.7 p3.1 01000 p2.0 p3.4 01001 p2.1 p3.5 01010 p2.2 p3.7 01011 p2.3 p4.0 01100 p2.4 p4.3 01101 p2.5 p4.4 01110 p2.6 p4.5 01111 p2.7 p4.6 10000 p3.0 reserved 10001 p0.0 p0.3 10010 p0.1 p0.4 10011 p0.4 p1.1 10100 p0.5 p1.2 10101 - 11101 reserved reserved 11110 temp sensor temp sensor 11111 v dd v dd
rev. 1.3 49 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 5.2. amx0n: amux0 negative channel select bits7?5: unused. read = 000b; write = don?t care. bits4?0: amx0n4?0: amux0 negative input selection. note that when gnd is selected as the nega tive input, adc0 operates in single-ended mode. for all other negative input select ions, adc0 operates in differential mode. r r r r/w r/w r/w r/w r/w reset value - - - amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xba amx0n4-0 adc0 negative input (32-pin package) adc0 negative input (48-pin package) 00000 p1.0 p2.0 00001 p1.1 p2.1 00010 p1.2 p2.2 00011 p1.3 p2.3 00100 p1.4 p2.5 00101 p1.5 p2.6 00110 p1.6 p3.0 00111 p1.7 p3.1 01000 p2.0 p3.4 01001 p2.1 p3.5 01010 p2.2 p3.7 01011 p2.3 p4.0 01100 p2.4 p4.3 01101 p2.5 p4.4 01110 p2.6 p4.5 01111 p2.7 p4.6 10000 p3.0 reserved 10001 p0.0 p0.3 10010 p0.1 p0.4 10011 p0.4 p1.1 10100 p0.5 p1.2 10101 - 11101 reserved reserved 11110 vref vref 11111 gnd (single-ended mode) gnd (single-ended mode)
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 50 rev. 1.3 sfr definition 5.3. adc0cf: adc0 configuration sfr definition 5.4. adc0h: adc0 data word msb sfr definition 5.5. adc0l: adc0 data word lsb bits7?3: ad0sc4?0: adc0 sar co nversion clock period bits. sar conversion clock is derived from syst em clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4-0. sar conversion clock requirements are given in table 5.1. bit2: ad0ljst: adc0 le ft justify select. 0: data in adc0h:adc0l re gisters are right-justified. 1: data in adc0h:adc0l re gisters are left-justified. bits1?0: unused. read = 00b; write = don?t care. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0sc4 ad0sc3 ad0sc2 ad0sc1 ad0sc0 ad0ljst - - 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbc ad0sc sysclk clk sar --------------------- - 1? = bits7?0: adc0 data word high-order bits. for ad0ljst = 0: bits 7?2 are the sign extension of bit1. bits 1-0 are the upper 2 bits of the 10-bit adc0 data word. for ad0ljst = 1: bits 7?0 are the most-signifi cant bits of the 10-bit adc0 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbe bits7?0: adc0 data word low-order bits. for ad0ljst = 0: bits 7?0 are the lower 8 bits of the 10-bit data word. for ad0ljst = 1: bits 7?6 are the lower 2 bits of the 10-bit data word. bits 5?0 will always read ?0?. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbd
rev. 1.3 51 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 5.6. adc0cn: adc0 control bit7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit6: ad0tm: adc0 track mode bit. 0: normal track mode: when adc0 is enabled, tracking is continuous unless a conversion is in progress. 1: low-power track mode: tracking defi ned by ad0cm2-0 bits (see below). bit5: ad0int: adc0 conversi on complete interrupt flag. 0: adc0 has not completed a data conversion since the last time ad0int was cleared. 1: adc0 has completed a data conversion. bit4: ad0busy: adc0 busy bit. read: 0: adc0 conversion is complete or a conversion is not currently in pr ogress. ad0int is set to logic 1 on the falling edge of ad0busy. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conversion if ad0cm2-0 = 000b bit3: ad0wint: adc0 window compare interrupt flag. 0: adc0 window comparison data match has no t occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bits2?0: ad0cm2?0: adc0 start of conversion mode select. when ad0tm = 0: 000: adc0 conversion initiated on every write of ?1? to ad0busy. 001: adc0 conversion initiated on overflow of timer 0. 010: adc0 conversion initiate d on overflow of timer 2. 011: adc0 conversion initia ted on overflow of timer 1. 100: adc0 conversion initiated on rising edge of external cnvstr. 101: adc0 conversion initiated on overflow of timer 3. 11x: reserved. when ad0tm = 1: 000: tracking initia ted on write of ?1? to ad0b usy and lasts 3 sar clocks, followed by conversion. 001: tracking initiated on overflow of timer 0 and lasts 3 sar clocks, followed by conversion. 010: tracking initiated on overflow of timer 2 and lasts 3 sar clocks, followed by conversion. 011: tracking initiated on overflow of timer 1 and lasts 3 sar clocks, followed by conversion. 100: adc0 tracks only when cnvst r input is logic low; conversi on starts on rising cnvstr edge. 101: tracking initiated on overflow of timer 3 and lasts 3 sar clocks, followed by conversion. 11x: reserved. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0en ad0tm ad0int ad0busy ad0wi nt ad0cm2 ad0cm1 ad0cm0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe8
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 52 rev. 1.3 5.4. programmable window detector the adc programmable window detector continuous ly compares the adc0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. this is especially effective in an interrupt-driven system, saving co de space and cpu bandwidth while delivering faster sys - tem response times. the window detector interrupt flag (a d0wint in register a dc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison valu es. the window detector flag can be programmed to indicate when mea - sured data is inside or outside of the user-program med limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. the window detector registers must be written with the same format (left/right ju stified, signed/unsigned) as that of the current adc configuration (lef t/right justified, sing le-ended/differential). sfr definition 5.7. adc0gth: adc0 greater-than data high byte sfr definition 5.8. adc0gtl: adc0 greater- than dat a low byte bits7?0: high byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc4 bits7?0: low byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc3
rev. 1.3 53 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 5.9. adc0lth: adc0 less-than data high byte sfr definition 5.10. adc0ltl: adc0 less-than data low byte bits7?0: high byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc6 bits7?0: low byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc5
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 54 rev. 1.3 5.4.1. window detector in single-ended mode figure 5.6 shows two example window comparisons fo r r ight-justified, single-ended data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). in single-ended mode, the input voltage can range from ?0? to vref x (1023/ 1024) with respect to gnd, and is represented by a 10-bit unsigned intege r value. in the left example, an ad0win t interrupt will be gener ated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the right example, and ad0wint interrupt will be generated if the adc0 conversion word is outside of the range defi ned by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 5.7 shows an exam - ple using left-justified data with equivale nt adc0gt and adc0lt register settings. figure 5.6. adc window co mpare example: right-justified single-ended data figure 5.7. adc window co mp are example: left-justified single-ended data 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl
rev. 1.3 55 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 5.4.2. window detector in differential mode figure 5.8 shows two example window comparisons for r ight-justified, differential data, with adc0lth:adc0ltl = 0x0040 (+64d) and adc0gth:adc0gth = 0xffff (-1d). in differential mode, the me asurable voltage between the input pins is between -vref and vref*(511/512). output codes are rep - resented as 10-bit 2?s complement s igned integers. in the left example, an ad 0wint interrupt will be gen - erated if the adc0 conversion wo rd (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0xffff (-1d) < adc0h:adc0l < 0x0040 (64d)). in the ri g ht example, an ad0wint interrupt will be generated if the adc0 conversion word is ou tside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0xffff (-1d) or adc0h:adc0l > 0x0040 (+64d)). figure 5.9 shows an example using left-justified data with equivalent adc0gt and adc0lt register set - tings. figure 5.8. ad c window compare example: righ t-justified differential data figure 5.9. adc window compare exampl e: lef t-justified differential data 0x01ff 0x0041 0x0040 0x003f 0x0000 0xffff 0xfffe 0x0200 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) 0x01ff 0x0041 0x0040 0x003f 0x0000 0xffff 0xfffe 0x0200 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0x7fc0 0x1040 0x1000 0x0fc0 0x0000 0xffc0 0xff80 0x8000 -vref input voltage (px.x - px.y) vref x (511/512) vref x (64/512) vref x (-1/512) 0x7fc0 0x1040 0x1000 0x0fc0 0x0000 0xffc0 0xff80 0x8000 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl ad0wint not affected adc0gth:adc0gtl ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 56 rev. 1.3 table 5.1. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v, ?40 to +85 c unless otherwise specified parameter conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity 0.5 1 lsb differential nonlinearity guaranteed monotonic 0.5 1 lsb offset error ?15 0 +15 lsb full scale error ?15 ?1 +15 lsb offset temperature coefficient 10 ppm/c dynamic performance (10 khz sine-wave single -en ded input, 1 db below full scale, 200 ksps) signal-to-noise plus distortion 51 52.5 db total harmonic distortion up to the 5 th harmonic ?67 db spurious-free dynamic range 78 db conversion rate sar conversion clock 3 mhz conversion time in sar clocks 10 clocks track/hold acquisition time 300 ns throughput rate 200 ksps analog inputs adc input voltage range single ended (ain+ ? gnd) differential (ain+ ? ain?) 0 ?vref vref vref v v absolute pin voltage with respect to g nd single ended or differential 0 v dd v input capacitance 5 pf temperature sensor linearity 1 0.1 c gain 2.86 mv/c gain error 2 33.5 v/oc offset 1 (temp = 0 c) 776 mv offset error 2 8.51 mv power specifications power supply current (v dd sup - plied to adc0) operating mode, 200 ksps 400 900 a power supply rejection 0.3 mv/v notes: 1. includes adc offset, gain, and linearity variations. 2. re presents one standard deviation from the mean.
rev. 1.3 57 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 6. voltage reference (c8051f340 /1/2/3/4/5/6/7/a/b only) the voltage reference mux on c8051f34x devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator, or the power supply voltage v dd (see figure 6.1 ). the refsl bit in the reference control register (ref0cn) selects the reference source. for the internal refer - ence or an external source, refsl should be set to ?0?; for v dd as the reference source, refsl should be set to ?1?. the biase bit enables the inte rnal adc bias generator, wh ich is used by the adc and internal oscillator. this enable is forced to logic 1 when either of t he aforementioned peripherals is enabled. the adc bias generator may be e nabled manually by writing a ?1? to the biase bit in register ref0cn; see sfr defini - tion 6.1 for ref0cn register details. th e re ference bias generator (see figure 6.1 ) is used by the internal voltage reference, temperature sensor, and clock multiplier . the reference bias is automatically enabled when any of the aforementioned peripherals are enabled. the electrical specifications for the volt - age reference and bias circuits are given in ta b l e 6.1 . important note about the vref pin: t he vref pin, when not using the on-chip voltage reference or an external precision reference, can be configured as a gpio port pin. when using an external voltage refer - ence or the on-chip reference, the vref pin should be configured as analog pin and skipped by the digital crossbar. to configure the vref pin for analog mode, set the corresponding bit in the pnmdin register to ?0?. to configure the crossbar to skip the vref pin, set the corresponding bit in register pnskip to ?1?. refer to section ?15. port input/output? on page 142 for complete port i/o configuration details. the temperature sensor connects to the adc0 positive input multiplexer (see section ?5.1. analog multi - plexer? on page 42 for details). the tempe bit in register ref0cn enables/disables the temperature sensor. while disabled, the temperature sensor defaults to a high impedance state and any adc0 mea - surements performed on the sensor result in meaningless data. figure 6.1. voltage refere nce functional block diagram vref (to adc) to analog mux vdd vref r1 vdd external voltage reference circuit gnd temp sensor en 0 1 ref0cn refsl tempe biase refbe refbe internal reference en reference bias en clkmul enable tempe to clock multiplier, temp sensor adc bias to adc, internal oscillator en ioscen ad0en
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 58 rev. 1.3 sfr definition 6.1. ref0cn: reference control table 6.1. voltage reference electrical characteristics v dd = 3.0 v; ?40 to +85 c unless otherwise specified parameter conditions min typ max units internal reference (refbe = 1) output voltage 25 c ambient 2.38 2.44 2.50 v vref short-circuit current 10 ma vref temperature coeffi - cient 15 ppm/c load regulation load = 0 to 200 a to gnd 1.5 ppm/a vref turn-on time 1 4.7 f tantalum, 0.1 f ceramic byp ass 2 ms vref turn-on time 2 0.1 f ceramic bypass 20 s vref turn-on time 3 no bypass cap 10 s power supply rejection 140 ppm/v external reference (refbe = 0) input voltage range 0 v dd v input current sample rate = 200 ksps; vref = 3.0 v 12 a bias generators adc bias generator biase = ?1? 100 a reference bias generator 40 a bits7?3: unused. read = 000 00b; write = don?t care. bit3: refsl: voltage reference select. this bit selects the source for the internal voltage reference. 0: vref pin used as voltage reference. 1: v dd used as voltage reference. bit2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. bit1: biase: internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. bit0: refbe: internal refe rence buffer enable bit. 0: internal reference buffer disabled. 1: internal reference buffer enabled. internal voltage reference driven on the vref pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - refsl tempe biase refbe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd1
rev. 1.3 59 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 7. comparators c8051f34x devices include two on-chip programmable voltage comparators. a block diagram of the com - parators is shown in figure 7.1 , where ?n? is the comparator number (0 or 1). the two comparators oper - ate identically with the following exceptions: (1) their input selections differ, and (2) comparator0 can be u sed as a reset source. for input selection details, refer to sfr definition 7.2 and sfr definition 7.5 . each comparator offers programmable response time and hysteresis, an analog input multiplexer, and two o utputs that are optionally available at the port pins : a synchronous ?latched? output (cp0, cp1), or an asynchronous ?raw? output (cp0a, cp1a). the asynchronous signal is available even when the system clock is not active. this allows the comparators to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator outputs may be configured as open drain or push-pull (see section ?15.2. port i/o initialization? on page 147 ). comparator0 may also be used as a reset source (see section ?11.5. comparator0 reset? on page 103 ). the comparator0 inputs are selected in the cpt0mx register ( sfr definition 7.2 ). the cmx0p1-cmx0p0 bits select the comparator0 positive input; the cmx0n1- cmx0n0 bits select the comparator0 negative input. the comparator1 inputs are selected in the cpt1mx register ( sfr definition 7.5 ). the cmx1p1-cmx1p0 bits select the comparator1 positive input; the cmx1n1-cmx1n0 bits select the co mparator1 negative input. important note about comparator inputs: th e port pins selected as comparator inputs should be con - figured as analog inputs in their associated port co nfigur ation register, and configured to be skipped by the crossbar (for details on port configuration, see section ?15.3. general purpose port i/o? on page 150 ).
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 60 rev. 1.3 figure 7.1. comparator functional block diagram comparator outputs can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, compar ator outputs are availa ble asynchronous or syn chronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis - abled, the comparator output (if assigned to a port i/o pin via th e crossbar) defaults to the logic low state, and supply current falls to less than 100 na. see section ?15.1. priority crossbar decoder? on page 144 for details on configuring comparator outputs vi a the dig ital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator elec - trical specifications are given in ta b l e 7.1 . comparator response time may be configured in software via the cptnmd registers (see sfr definition 7.3 and sfr definition 7.6 ). selecting a longer response time re duce s the comparator supply current. see ta b l e 7.1 for complete timing and supply current specifications. vdd cptncn reset decision tree (comprator 0 only) + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cpn + cpn - cpnen cpnout cpnrif cpnfif cpnhyp1 cpnhyp0 cpnhyn1 cpnhyn0 cptnmd cpnrie cpnfie cpnmd1 cpnmd0 cpn cpna cpn rising-edge cpn falling-edge cpn interrupt cpnrie cpnfie cptnmx cmxnn1 cmxnn0 cmxnp1 cmxnp0 cmxnn2 cmxnp2 port i/o connection options vary with package (32-pin or 48-pin)
rev. 1.3 61 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 7.2. compar ator hysteresis plot comparator hysteresis is programmed using bits3-0 in the comparator control register cptncn (shown in sfr definition 7.1 and sfr definition 7.4 ). the amount of negative hyst er esis voltage is determined by the settings of the cpnhyn bits. as shown in figure 7.2 , various levels of negative hysteresis can be programmed, or negative hysteresis can be disabled. in a sim ilar way, the amount of positive hysteresis is determined by the setting the cpnhyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter - rupt enable and priority control, see section ?9.3. interrupt handler? on page 88 .) the cpnfif flag is set to ?1? upon a comparator fa lling-edge, and the cpnrif flag is set to ?1? upon the comparator rising-edge. once set, these bits remain set until cleared by so ftware. the output state of the comparator can be obtained at any time by reading the cpnout bit. th e comparator is enabled by setting the cpnen bit to ?1?, and is disabled by clearing this bit to ?0?. positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 62 rev. 1.3 sfr definition 7.1. cpt0cn: comparator0 control bit7: cp0en: comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. bit6: cp0out: comparator0 output state flag. 0: voltage on cp0+ < cp0?. 1: voltage on cp0+ > cp0?. bit5: cp0rif: comparator0 rising-edge flag. 0: no comparator0 rising edge has occurr ed since this flag was last cleared. 1: comparator0 rising edge has occurred. bit4: cp0fif: comparator0 falling-edge flag. 0: no comparator0 falling-e dge has occurred since this flag was last cleared. 1: comparator0 falling-edge interrupt has occurred. bits3?2: cp0hyp1?0: comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1?0: cp0hyn1?0: comparator0 nega tive hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. r/w r r/w r/w r/w r/w r/w r/w reset value cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9b
rev. 1.3 63 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 7.2. cpt0mx: comparator0 mux selection bit7: unused. read = 0b, write = don?t care. bits6?4: cmx0n2?cmx0n0: comparator0 negative input mux select. these bits select which port pin is used as the comparator0 negative input. bit3: unused. read = 0b, write = don?t care. bits2?0: cmx0p2?cmx0p0: comparator0 positive input mux select. these bits select which port pin is used as the comparator0 positive input. note that the port pins used by the comparator depend on the package type (32-pin or 48-pin). r/w r/w r/w r/w r/w r/w r/w r/w reset value - cmx0n2 cmx0n1 cmx0n0 - cmx0p2 cmx0p1 cmx0p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9f cmx0n1 cmx0n1 cmx0n0 negative input (32-pin package) negative input (48-pin package) 0 0 0 p1.1 p2.1 0 0 1 p1.5 p2.6 0 1 0 p2.1 p3.5 0 1 1 p2.5 p4.4 1 0 0 p0.1 p0.4 cmx0p1 cmx0p1 cmx0p0 positive input (32-pin package) positive input (48-pin package) 000 p1.0 p2.0 001 p1.4 p2.5 010 p2.0 p3.4 011 p2.4 p4.3 100 p0.0 p0.3
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 64 rev. 1.3 sfr definition 7.3. cpt0md: comparator 0 mode selection bits7?6: unused. read = 00b. write = don?t care. bit5: cp0rie: comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. bit4: cp0fie: comparator0 falling-edge interrupt enable. 0: comparator0 falling-ed ge interrupt disabled. 1: comparator0 falling-ed ge interrupt enabled. bits3?2: unused. read = 00b. write = don?t care. bits1?0: cp0md1?cp0md0: comparator0 mode select these bits select the response time for comparator0. * see table 7.1 for response time parameters. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - cp0rie cp0fie - - cp0md1 cp0md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9d mode cp0md1 cp0md0 cp0 response time* 0 0 0 fastest response 101 210 311 lowest power
rev. 1.3 65 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 7.4. cpt1cn: comparator1 control bit7: cp1en: comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. bit6: cp1out: comparator1 output state flag. 0: voltage on cp1+ < cp1?. 1: voltage on cp1+ > cp1?. bit5: cp1rif: comparator1 rising-edge flag. 0: no comparator1 rising edge has occurr ed since this flag was last cleared. 1: comparator1 rising edge has occurred. bit4: cp1fif: comparator1 falling-edge flag. 0: no comparator1 falling-e dge has occurred since this flag was last cleared. 1: comparator1 falling-edge has occurred. bits3?2: cp1hyp1?0: comparator1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1?0: cp1hyn1?0: comparator1 nega tive hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. r/w r r/w r/w r/w r/w r/w r/w reset value cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9a
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 66 rev. 1.3 sfr definition 7.5. cpt1mx: comparator1 mux selection bit7: unused. read = 0b , write = don?t care. bits6?4: cmx1n2?cmx1n0: comparat or1 negative input mux select. these bits select which port pin is us ed as the comparator1 negative input. bit3: unused. read = 0b , write = don?t care. bits2?0: cmx1p1?cmx1p0: comparator1 positive input mux select. these bits select which port pin is us ed as the comparator1 positive input. note that the port pins used by the comparator depend on the package type (32-pin or 48-pin). r/w r/w r/w r/w r/w r/w r/w r/w reset value - cmx1n2 cmx1n1 cmx1n0 - cmx1p2 cmx1p1 cmx1p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9e cmx1n2 cmx1n1 cmx1n0 negative input (32-pin package) negative input (48-pin package) 000 p1.3 p2.3 001 p1.7 p3.1 010 p2.3 p4.0 011 p2.7 p4.6 100 p0.5 p1.2 cmx1p2 cmx1p1 cmx1p0 positive input (32-pin package) positive input (48-pin package) 0 0 0 p1.2 p2.2 0 0 1 p1.6 p3.0 0 1 0 p2.2 p3.7 0 1 1 p2.6 p4.5 1 0 0 p0.4 p1.1
rev. 1.3 67 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 7.6. cpt1md: comparator 1 mode selection bits7?6: unused. read = 00b, write = don?t care. bit5: cp1rie: comparator1 rising-edge interrupt enable. 0: comparator1 rising-edge interrupt disabled. 1: comparator1 rising-edge interrupt enabled. bit4: cp1fie: comparator1 falling-edge interrupt enable. 0: comparator1 falling-ed ge interrupt disabled. 1: comparator1 falling-ed ge interrupt enabled. bits1?0: cp1md1?cp1md0: comparator1 mode select. these bits select the response time for comparator1. * see table 7.1 for response time parameters. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - cp1rie cp1fie - - cp1md1 cp1md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9c mode cp1md1 cp1md0 cp1 response time* 0 0 0 fastest response 101 210 311 lowest power
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 68 rev. 1.3 table 7.1. comparator electri cal characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise noted. all specifications apply to both comparator0 and comparator1 unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm* = 1.5 v cp0+ ? cp0? = 100 mv 100 ns cp0+ ? cp0? = ?100 mv 250 ns response time: mode 1, vcm* = 1.5 v cp0+ ? cp0? = 100 mv 175 ns cp0+ ? cp0? = ?100 mv 500 ns response time: mode 2, vcm* = 1.5 v cp0+ ? cp0? = 100 mv 320 ns cp0+ ? cp0? = ?100 mv 1100 ns response time: mode 3, vcm* = 1.5 v cp0+ ? cp0? = 100 mv 1050 ns cp0+ ? cp0? = ?100 mv 5200 ns common-mode rejection ratio 1.5 4 mv/v positive hysteresis 1 cp0hyp1?0 = 00 0 1 mv positive hysteresis 2 cp0hyp1?0 = 01 2 5 10 mv positive hysteresis 3 cp0hyp1?0 = 10 7 10 20 mv positive hysteresis 4 cp0hyp1?0 = 11 15 20 30 mv negative hysteresis 1 cp0hyn1?0 = 00 0 1 mv negative hysteresis 2 cp0hyn1?0 = 01 2 5 10 mv negative hysteresis 3 cp0hyn1?0 = 10 7 10 20 mv negative hysteresis 4 cp0hyn1?0 = 11 15 20 30 mv inverting or non-inverting inpu t voltage range ?0.25 v dd + 0.25 v input capacitance 3 pf input bias current 0.001 na input offset voltage ?5 +5 mv power supply power supply rejection 0.1 mv/v power-up time 10 s supply current at dc mode 0 7.6 a mode 1 3.2 a mode 2 1.3 a mode 3 0.4 a *note: vcm is the common-mode voltage on cp0+ and cp0?.
rev. 1.3 69 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 8. voltage regulator (reg0) c8051f34x devices include a voltage regulator (reg0). when enabled, the reg0 output appears on the v dd pin and can be used to power external devices. reg0 can be enabled/disabled by software using bit regen in register reg0cn. see ta b l e 8.1 for reg0 electrical characteristics. note that the vbus signal must be connected to th e vbus pin when using the device in a usb network. the vbus signal should only be connected to the re gin pin when operating the device as a bus-powered function. reg0 configuration options are shown in figure 8.1 ? figure 8.4 . 8.1. regulator mode selection reg0 offers a low power mode intended for use when the device is in suspend mode. in this low power mode, the reg0 output remains as specified; however the reg0 dynami c performance (response time) is degraded. see ta b l e 8.1 for normal and low power mode supply cu rrent specificati ons. the reg0 mode selection is controlled via the regmod bit in register reg0cn. 8.2. vbus detection when the usb function controller is used (see section section ?16. universal serial bus controller (usb0)? on page 159 ), the vbus signal should be connected to the vbus pin. the vbstat bit (register reg0cn) indicates the current logic level of the vbus s ignal. if enabled, a vbus interrupt will be gener - ated when the vbus signal matches the polarity selected by the vbpo l bit in register reg0cn. the vbus interrupt is level-sensitive, and has no asso ciated interrup t pending flag. the vbus interrupt will be active as long as the vbus signal matc hes the polarity selected by vbpol. see ta b l e 8.1 for vbus input parameters. important note: when usb is selected as a reset source , a system reset will be generated when the vbus signal matches the polarity selected by the vbpol bit. see section ?11. reset sources? on page 100 for details on selecting usb as a reset source table 8.1. voltage regulator elect rical s pecifications ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range 1 2.7 5.25 v output voltage (v dd ) 2 output current = 1 to 100 ma 3.0 3.3 3.6 v output current 2 100 ma vbus detection input low voltage 1.0 v vbus detection input high voltage 3.0 v bias current normal mode (regmod = ?0?) low power mode (regmod = ?1?) 65 35 111 61 a dropout voltage (v do ) 3 1 mv/ma notes: 1. inpu t range specified for regulation. when an exte rnal regulator is used, should be tied to v dd . 2. output cu rrent is total regulator output, in cluding any current required by the c8051f34x. 3. t he minimum input voltage is 2.70 v or vdd + v do (max load), whichever is greater.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 70 rev. 1.3 figure 8.1. reg0 confi guration: usb bus-powered figure 8.2. reg0 configuration: usb self-powered voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus from vbus to 3 v power net device power net vdd voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus to 3 v power net device power net vdd from 5 v power net from vbus
rev. 1.3 71 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 8.3. reg0 conf iguration: usb self-pow ered, regulator disabled figure 8.4. reg0 configur ation: no usb connection voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus from 3 v power net device power net vdd from vbus voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus to 3 v power net device power net vdd from 5 v power net
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 72 rev. 1.3 sfr definition 8.1. reg0cn: voltage regulator control bit7: regdis: voltag e regulator disable. 0: voltage regulator enabled. 1: voltage regulator disabled. bit6: vbstat: vbus signal status. 0: vbus signal currently absent (device not attached to usb network). 1: vbus signal currently present (device attached to usb network). bit5: vbpol: vbus interr upt polarity select. this bit selects the vbus interrupt polarity. 0: vbus interrupt acti ve when vbus is low. 1: vbus interrupt active when vbus is high. bit4: regmod: voltage re gulator mode select. this bit selects the voltage regulator mode. when regmod is set to ?1?, the voltage regu- lator operates in low power (suspend) mode. 0: usb0 voltage regulator in normal mode. 1: usb0 voltage regula tor in low power mode. bits3?0: reserved. read = 0000b. must write = 0000b. r/w r r/w r/w r/w r/w r/w r/w reset value regdis vbstat vbpol regmod reserved r eserved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc9
rev. 1.3 73 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 9. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft - ware. the mcu family has a superset of all the peripherals included with a standard 8051. included are fou r 16-bit counter/timers (see description in section 21 ), an enhanced full-duplex uart (see description in section 18 ), an enhanced spi (see description in section 20 ), 256 bytes of internal ram, 128 byte special function register (sfr) address space ( section 9.2.6 ), and 25 port i/o (see description in sec - tion 15 ). the cip-51 also includes on-chip debug hardware (see description in section 23 ), and interfaces directly with the analog and digi t al subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional c ustom peripherals and func tions to extend its capability (see figure 9.1 for a block diagram). the cip-51 includes the following features: figure 9.1. cip-51 block diagram - fully compatible wit h mcs-51 instruction set - 0 to 48 mhz clock frequency - 256 bytes of internal ram - 25 port i/o - extended interrupt handler - reset input - power management modes - on-chip debug logic - program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 74 rev. 1.3 performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core exec utes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that for execution time. programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is ac complished via the silicon labs 2-wire de velopment interface (c2). note that the re-program - mable flash can also be read and changed a single by te at a time by the application software using the movc and movx instructions. this feature allows program memory to be used for non-volatile data stor - age as well as updating program code under software control. the on-chip silicon labs 2- wire (c2) d evelopment interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions , allowing in-system debugging with - out occupying package pins. c2 details can be found in section ?23. c2 interface? on page 271 . the cip-51 is support ed by devel opment tools from silicon labs and third party vendors. silicon labs pro - vides an integrated development environment (ide) including editor, debugger, and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast and efficient in-system device programming and debugging. an 8051 assembler, lin ker and evaluation ?c? compiler are included in the development kit. many third party ma cro assemblers and c compilers are also available, which can be used directly with the ide. 9.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc - tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 in structions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan - dard 8051. 9.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most in structions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instructions take two fewer clock cycles to complete when the branch is not taken as opposed to when the branch is taken. ta b l e 9.1 is the cip-51 instruction set summary, which includes the mn emonic, number of bytes, and number of clock cycles for each instruction. clocks to execute 1 2 2/4 3 3/5 4 5 4/6 6 8 number of instructions 26 50 5 10 7 5 2 1 2 1
rev. 1.3 75 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 9.1.2. movx instruction and program memory in the cip-51, the movx instruction serves three pur poses: accessing on-chip xram, accessing off-chip data xram (only on c8051f340/1/4/5/8 devices), and accessing on-chip program flash memory. the flash access feature provides a mechanism for user software to update program code and use the pro - gram memory space for non-volatile data storage (see section ?12. flash memory? on page 107 ). the external memory interface (only on c8051f340/1/4/5/8 devices) provides a fast access interface to of f-chip data xram (or memory-mapped peripherals) via the movx instruction. refer to section ? 13. external data memory interface and on-chip xram ? on page 114 . for details. table 9.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 76 rev. 1.3 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 table 9.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
rev. 1.3 77 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/4 jnc rel jump if carry is not set 2 2/4 jb bit, rel jump if direct bit is set 3 3/5 jnb bit, rel jump if direct bit is not set 3 3/5 jbc bit, rel jump if direct bit is set and clear bit 3 3/5 program branching acall addr11 absolute subroutine call 2 4 lcall addr16 long subroutine call 3 5 ret return from subroutine 1 6 reti return from interrupt 1 6 ajmp addr11 absolute jump 2 4 ljmp addr16 long jump 3 5 sjmp rel short jump (relative address) 2 4 jmp @a+dptr jump indirect relative to dptr 1 4 jz rel jump if a equals zero 2 2/4 jnz rel jump if a does not equal zero 2 2/4 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/5 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/5 cjne rn, #data, rel compare immediate to register and jump if not equal 3 3/5 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 4/6 djnz rn, rel decrement register and jump if not zero 2 2/4 djnz direct, rel decrement direct byte and jump if not zero 3 3/5 nop no operation 1 1 table 9.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 78 rev. 1.3 notes on registers, operands and addressing modes: rn - register r0-r7 of the currently selected register bank. @ri - data ram location address ed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00-0x7f) or an sfr (0x80-0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2k-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 8k-byte program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
rev. 1.3 79 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 9.2. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different in struction types. the cip-51 memory organization is shown in figure 9.2 and figure 9.3 . figure 9.2. on-chip memo ry map for 64 kb devices program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 4096 bytes (accessable using movx instruction) 0x0000 0x0fff off-chip xram (available only on devices with emif) 0x0400 0xffff flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0xfc00 0xfbff usb fifos 1024 bytes 0x07ff 0x1000 0xffff
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 80 rev. 1.3 figure 9.3. on-chip memo ry map for 32 kb devices 9.2.1. program memory the cip-51 core has a 64k-byte program memory space. the c8051f34x implements 64k or 32k bytes of this program memory space as in-system, re-progra mmable flash memory. note that on the 64k versions of the c8051f34x, addresses above 0xfbff are reserved. program memory is normally assumed to be read-only . however, the cip-51 can write to program memory by setting the program store write enable bit (psctl.0) and using the movx instru ction. this feature pro - vides a mechanism for the cip-51 to update program code and use the program memory space for non-volatile dat a storage. refer to section ?12. flash memory? on page 107 for further details. program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 2048 bytes (accessable using movx instruction) 0x0000 0x07ff off-chip xram (available only on devices with emif) 0x0400 0xffff flash (in-system programmable in 512 byte sectors) 0x0000 0x7fff usb fifos 1024 bytes 0x07ff 0x0800
rev. 1.3 81 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 9.2.2. data memory the cip-51 includes 256 of internal ram mapped in to the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. eithe r direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0 x00 through 0x1f are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, may either be addressed as by tes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by i ndir ect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or th e sfrs. in structions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 9.2 illustrates the data memory organization of the cip-51. 9.2.3. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen - eral-purpose registers. each bank consists of eigh t b yte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in sfr definition 9.4 ). this allows fast context switching when entering subroutines and inte rrupt service routines. indirect addressing modes use registers r0 and r1 as index registers. 9.2.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x 00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0 x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina - tion). the mcs-51? assembly language allows an alternate no tation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22h.3 moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 9.2.5. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig - nated using the stack pointer (sp, 0x81) sfr. the sp will poin t to the last location used. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07. therefore, the first value pushed on the st ack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 82 rev. 1.3 9.2.6. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 805 1 implementation as well as implementing additional sfrs used to configure and access the sub-systems uni que to the mcu. this allows the addition of new functionality while retain ing compatibility with the mc s-51? instruction set. ta b l e 9.2 list s the sfrs imple - mented in the cip-51 system controller. the sfr registers are accessed anytime the direct ad dr essing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g. p0, tcon, scon0, ie, etc.) are bit-addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the datasheet, as indicated in ta b l e 9.3 , for a detailed description of each register. table 9.2. special function re gister (sfr) memory map f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 pca0cpl4 pca0cph4 vdm0cn f0 b p0mdin p1mdin p2mdin p 3mdin p4mdin eip1 eip2 e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 pca0cpl3 pca0cph3 rstsrc e0 acc xbr0 xbr1 xbr2 it01cf smod1 eie1 eie2 d8 pca0cn pca0md pca0cpm0 pca0cpm1 pc a0cpm2 pca0cpm3 pca0cpm4 p3skip d0 psw ref0cn scon1 sbuf1 p0skip p1skip p2skip usb0xcn c8 tmr2cn reg0cn tmr2rll tmr2rlh tmr2l tmr2h - - c0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth p4 b8 ip clkmul amx0n amx0p adc0cf adc0l adc0h - b0 p3 oscxcn oscicn oscicl sbrll1 sbrlh1 flscl flkey a8 ie clksel emi0cn - sbcon1 - p4mdout pfe0cn a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout p3mdout 98 scon0 sbuf0 cpt1cn cpt0cn cpt1md cpt0md cpt1mx cpt0mx 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h usb0adr usb0dat 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph emi0tc emi0cf osclcn pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable)
rev. 1.3 83 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d table 9.3. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address description page acc 0xe0 accumulator 87 adc0cf 0xbc adc0 configuration 50 adc0cn 0xe8 adc0 control 51 adc0gth 0xc4 adc0 greater-than compare high 52 adc0gtl 0xc3 adc0 greater-than compare low 52 adc0h 0xbe adc0 high 50 adc0l 0xbd adc0 low 50 adc0lth 0xc6 adc0 less-than compare word high 53 adc0ltl 0xc5 adc0 less-than compare word low 53 amx0n 0xba amux0 negative channel select 49 amx0p 0xbb amux0 positive channel select 48 b 0xf0 b register 88 ckcon 0x8e clock control 241 clkmul 0xb9 clock multiplier 138 clksel 0xa9 clock select 140 cpt0cn 0x9b comparator0 control 62 cpt0md 0x9d comparator0 mode selection 64 cpt0mx 0x9f comparator0 mux selection 63 cpt1cn 0x9a comparator1 control 65 cpt1md 0x9c comparator1 mode selection 67 cpt1mx 0x9e comparator1 mux selection 66 dph 0x83 data pointer high 86 dpl 0x82 data pointer low 86 eie1 0xe6 extended interrupt enable 1 93 eie2 0xe7 extended interrupt enable 2 95 eip1 0xf6 extended interrupt priority 1 94 eip2 0xf7 extended interrupt priority 2 95 emi0cn 0xaa external memory interface control 117 emi0cf 0x85 external memory interface configuration 118 emi0tc 0x84 external memory interface timing 123 flkey 0xb7 flash lock and key 112 flscl 0xb6 flash scale 113 ie 0xa8 interrupt enable 91 ip 0xb8 interrupt priority 92 it01cf 0xe4 int0/int1 configuration 96 oscicl 0xb3 internal oscillator calibration 133 oscicn 0xb2 internal oscillator control 132 osclcn 0x86 internal low-frequenc y oscillator control 134 oscxcn 0xb1 external oscillator control 137 p0 0x80 port 0 latch 150 p0mdin 0xf1 port 0 input mode configuration 150 p0mdout 0xa4 port 0 output mode configuration 151 p0skip 0xd4 port 0 skip 151 p1 0x90 port 1 latch 152
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 84 rev. 1.3 p1mdin 0xf2 port 1 input mode configuration 152 p1mdout 0xa5 port 1 output mode configuration 152 p1skip 0xd5 port 1 skip 153 p2 0xa0 port 2 latch 153 p2mdin 0xf3 port 2 input mode configuration 153 p2mdout 0xa6 port 2 output mode configuration 154 p2skip 0xd6 port 2 skip 154 p3 0xb0 port 3 latch 155 p3mdin 0xf4 port 3 input mode configuration 155 p3mdout 0xa7 port 3 output mode configuration 155 p3skip 0xdf port 3skip 156 p4 0xc7 port 4 latch 156 p4mdin 0xf5 port 4 input mode configuration 157 p4mdout 0xae port 4 output mode configuration 157 pca0cn 0xd8 pca control 266 pca0cph0 0xfc pca capture 0 high 270 pca0cph1 0xea pca capture 1 high 270 pca0cph2 0xec pca capture 2 high 270 pca0cph3 0xee pca capture 3high 270 pca0cph4 0xfe pca capture 4 high 270 pca0cpl0 0xfb pca capture 0 low 269 pca0cpl1 0xe9 pca capture 1 low 269 pca0cpl2 0xeb pca capture 2 low 269 pca0cpl3 0xed pca capture 3 low 269 pca0cpl4 0xfd pca capture 4 low 269 pca0cpm0 0xda pca module 0 mode register 268 pca0cpm1 0xdb pca module 1 mode register 268 pca0cpm2 0xdc pca module 2 mode register 268 pca0cpm3 0xdd pca module 3 mode register 268 pca0cpm4 0xde pca module 4 mode register 268 pca0h 0xfa pca counter high 269 pca0l 0xf9 pca counter low 269 pca0md 0xd9 pca mode 267 pcon 0x87 power control 98 pfe0cn 0xaf prefetch engine control 99 psctl 0x8f program store r/w control 112 psw 0xd0 program status word 87 ref0cn 0xd1 voltage reference control 58 reg0cn 0xc9 voltage regulator control 72 rstsrc 0xef reset source configuration/status 105 sbcon1 0xac uart1 baud rate generator control 220 sbrlh1 0xb5 uart1 baud rate generator high 221 sbrll1 0xb4 uart1 baud rate generator low 221 sbuf1 0xd3 uart1 data buffer 220 scon1 0xd2 uart1 control 218 table 9.3. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address description page
rev. 1.3 85 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sbuf0 0x99 uart0 data buffer 211 scon0 0x98 uart0 control 210 smb0cf 0xc1 smbus configuration 194 smb0cn 0xc0 smbus control 196 smb0dat 0xc2 smbus data 198 smod1 0xe5 uart1 mode 219 sp 0x81 stack pointer 86 spi0cfg 0xa1 spi configuration 229 spi0ckr 0xa2 spi clock rate control 231 spi0cn 0xf8 spi control 230 spi0dat 0xa3 spi data 231 tcon 0x88 timer/counter control 239 th0 0x8c timer/counter 0 high 242 th1 0x8d timer/counter 1 high 242 tl0 0x8a timer/counter 0 low 242 tl1 0x8b timer/counter 1 low 242 tmod 0x89 timer/counter mode 240 tmr2cn 0xc8 timer/counter 2 control 247 tmr2h 0xcd timer/counter 2 high 248 tmr2l 0xcc timer/counter 2 low 248 tmr2rlh 0xcb timer/counter 2 reload high 248 tmr2rll 0xca timer/counter 2 reload low 248 tmr3cn 0x91 timer/counter 3control 253 tmr3h 0x95 timer/counter 3 high 254 tmr3l 0x94 timer/counter 3low 254 tmr3rlh 0x93 timer/counter 3 reload high 254 tmr3rll 0x92 timer/counter 3 reload low 254 vdm0cn 0xff v dd monitor control 102 usb0adr 0x96 usb0 indirect address register 163 usb0dat 0x97 usb0 data register 164 usb0xcn 0xd7 usb0 transceiver control 161 xbr0 0xe1 port i/o crossbar control 0 148 xbr1 0xe2 port i/o crossbar control 1 149 xbr2 0xe3 port i/o crossbar control 2 149 all other addresses reserved table 9.3. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address description page
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 86 rev. 1.3 9.2.7. register descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic l. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default st ate. detailed descriptions of the remaining sfrs are included in the sections of the datasheet associated with their corresponding sys - tem function. sfr definition 9.1. dpl: data pointer low byte sfr definition 9.2. dph: data pointer high byte sfr definition 9.3. sp: stack pointer bits7?0: dpl: data pointer low. the dpl register is the low byte of the 16-b it dptr. dptr is used to access indirectly addressed memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x82 bits7?0: dph: data pointer high. the dph register is the high byte of the 16-b it dptr. dptr is used to access indirectly addressed memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x83 bits7?0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp r egister defaults to 0x07 after reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x81
rev. 1.3 87 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 9.4. psw: program status word sfr definition 9.5. acc: accumulator bit7: cy: carry flag. this bit is set when the last arithmetic operat ion resulted in a carry (addition) or a borrow (subtraction). it is cleared to logi c 0 by all other arithmetic operations. bit6: ac: auxiliary carry flag this bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arithmetic operations. bit5: f0: user flag 0. this is a bit-addressable, general purpose flag for use under software control. bits4?3: rs1?rs0: register bank select. these bits select which register ban k is used during register accesses. ? bit2: ov: overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instructi on causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, addc, subb, mul, and div inst ructions in all other cases. bit1: f1: user flag 1. this is a bit-addressable, general purpose flag for use under software control. bit0: parity: parity flag. this bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. r/w r/w r/w r/w r/w r/w r/w r reset value cy ac f0 rs1 rs0 ov f1 parity 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd0 rs1 rs0 register bank address 0 0 0 0x00 - 0x07 0 1 1 0x08 - 0x0f 1 0 2 0x10 - 0x17 1 1 3 0x18 - 0x1f bits7?0: acc: accumulator. this register is the accumulator for arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe0
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 88 rev. 1.3 sfr definition 9.6. b: b register 9.3. interrupt handler the cip-51 includes an extended interrupt system supp orting multiple interrupt sources with two priority levels. the allocation of interrupt sources between on -chip peripherals and external inputs pins varies according to the specific version of the device. each interrupt source has one or more associated inter - rupt-pending flag(s) located in an sfr. when a perip h eral or external source meets a valid interrupt condi - tion, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede - termined address to begin execution of an interrupt se rvice ro utine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal . (the interrupt-pending flag is set to logic 1 regard - less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or di sabled through the use of an associated interrupt enable bit in an sfr (ie-eie2). ho wever, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are re cogn ized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of th e next instruction. 9.3.1. mcu interrupt sources and vectors the mcu supports multiple interrup t sources. software ca n simulate an interrupt by setting any inter - rupt-pending flag to logic 1. if interrupts are enabled for the flag , an interrupt request will be generated and the cpu will vector to the isr addres s associated with the interrupt-pendi ng flag. mcu interrupt sources, associated vector addresses, priority or der and control bits are summarized in ta b l e 9.4 on page 90 . refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid in terrupt conditions for the peripheral and t he behavior of its interrupt-pending flag(s). 9.3.2. external interrupts the int0 and int1 external interrupt sources are configurable as active high or low, edge or level sensi - tive. the in0pl ( int0 polarity) and in1pl ( int1 polarity) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon ( section ?21.1. timer 0 and timer 1? on page 235 ) select level or edge sensitive. the following tabl e list s the possible configurations. bits7?0: b: b register. this register serves as a second accumu lator for certain arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xf0
rev. 1.3 89 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d int0 and int1 are assigned to port pins as defined in the it01cf register (see sfr definition 9.13 ). note that int0 and int0 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins wit hout disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section ?15.1. priority crossbar decoder? on page 144 for complete details on configuring the cro ssbar ). in the typical configuration, the external interrupt pin should be skipped in the crossbar and configured as open-drain with the pin latch set to '1'. ie0 (tcon.1) and ie1 (tcon.3) serve as the in terrupt-pending flags for the int0 and int1 external inter - rupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu ve ctors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); th e flag remains logic 0 while the input is inactive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt request befor e execution of the isr completes or another interrup t request will be generated. 9.3.3. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior - ity interrupt service routine can be pree mpted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip2) used to configure its priority level. low priority is th e default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in ta b l e 9.4 . 9.3.4. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 6 system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new in terrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the reti, 8 clock cyc les to complete the div instruction and 5 clock cycles to execute the lcall to the isr. if the cpu is ex ecuting an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. note that the cpu is stalled during flash write/ e rase operations and usb fifo movx accesses (see section ?13.2. accessing usb fifo space? on page 115 ). interrupt service latency will be increased for interrupts occurring while the cpu is st alled. the latency for these si tuations will be de termined by the standard interrupt service procedure (as described ab ove) and the amount of time the cpu is stalled. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 10 active low, edge sensitive 10 active low, edge sensitive 11 active high, edge sensitive 11 active high, edge sensitive 00 active low, level sensitive 00 active low, level sensitive 01 active high, level sensitive 01 active high, level sensitive
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 90 rev. 1.3 9.3.5. interrupt register descriptions the sfrs used to enable the interrupt sources and set t heir priority level are described below. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). table 9.4. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none n/a n/a always en abled always hig hest external interrupt 0 ( int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 ( int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) ? wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6 ) pspi0 (ip .6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1 .0) usb0 0x0043 8 special n n eusb0 (eie1.1) pusb0 (eip1 .1) adc0 window comp are 0x004b 9 ad0wint (adc0cn .3) y n ewadc0 (eie1.2) pwadc0 (eip1 .2) adc0 conversion complete 0x0053 10 ad0int (adc0cn.5) y n eadc0 (eie1.3) padc0 (eip1 .3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (eie1.4) ppca0 (eip1 .4) comparator0 0x0063 12 cp0fif (cpt0cn.4) c p0rif (cpt0cn.5) n n ecp0 (eie1.5) pcp0 (eip1 .5) comparator1 0x006b 13 cp1fif (cpt1cn.4) c p1rif (cpt1cn.5) n n ecp1 (eie1.6) pcp1 (eip1 .6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.7) pt3 (eip1 .7) vbus level 0x007b 15 n/a n/a n/a evbus (eie2.0) pvbus (eip2 .0) uart1 0x0083 16 ri1 (scon1.0) ti1 (scon1.1) n n es1 (eie2.1) ps1 (eip2 .1)
rev. 1.3 91 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 9.7. ie: interrupt enable bit7: ea: enable all interrupts. this bit globally enables/disabl es all interrupts. it overrides the individual interrupt mask set- tings. 0: disable all interrupt sources. 1: enable each interrupt accord ing to its individual mask setting. bit6: espi0: enable seri al peripheral interf ace (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. bit5: et2: enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. bit4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable ua rt0 interrupt. bit3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all ti mer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. bit2: ex1: enable exte rnal interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. bit1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all ti mer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. bit0: ex0: enable exte rnal interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input. r/w r/w r/w r/w r/w r/w r/w r/w reset value ea espi0 et2 es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa8
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 92 rev. 1.3 sfr definition 9.8. ip: interrupt priority bit7: unused. read = 1, write = don't care. bit6: pspi0: serial periph eral interface (spi0) in terrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. bit5: pt2: timer 2 interr upt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupts set to high priority level. bit4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupts set to high priority level. bit3: pt1: timer 1 interr upt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupts set to high priority level. bit2: px1: external interr upt 1 priority control. this bit sets the priority of the ex ternal interrupt 1 interrupt. 0: external interrupt 1 set to low priority level. 1: external interrupt 1 set to high priority level. bit1: pt0: timer 0 interr upt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. bit0: px0: external interr upt 0 priority control. this bit sets the priority of the ex ternal interrupt 0 interrupt. 0: external interrupt 0 set to low priority level. 1: external interrupt 0 set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value - pspi0 pt2 ps0 pt1 px1 pt0 px0 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb8
rev. 1.3 93 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 9.9. eie1: extended interrupt enable 1 bit7: et3: enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. bit6: ecp1: enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1rif or cp1fif flags. bit5: ecp0: enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. bit4: epca0: enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. bit3: eadc0: enable adc0 co nversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conver sion complete interrupt. 1: enable interrupt requests generated by the ad0int flag. bit2: ewadc0: enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (ad0wint). bit1: eusb0: enable usb0 interrupt. this bit sets the masking of the usb0 interrupt. 0: disable all u sb0 interrupts. 1: enable interrupt requests generated by usb0. bit0: esmb0: enable smbu s (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0. r/w r/w r/w r/w r/w r/w r/w r/w reset value et3 ecp1 ecp0 epca0 eadc0 ewadc0 eusb0 esmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe6
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 94 rev. 1.3 sfr definition 9.10. eip1: extended interrupt priority 1 bit7: pt3: timer 3 interr upt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts se t to low priority level. 1: timer 3 interrupts set to high priority level. bit6: pcp1: comparator1 (cp1) interrupt prio rity control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. bit5: pcp0: comparator0 (cp0) interrupt prio rity control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. bit4: ppca0: programmable counter arra y (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. bit3: padc0 adc0 conversion comp lete interrupt pr iority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete inte rrupt set to high priority level. bit2: pwadc0: adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt set to low priority level. 1: adc0 window interrupt set to high priority level. bit1: pusb0: usb0 interr upt priority control. this bit sets the priority of the usb0 interrupt. 0: usb0 interrupt set to low priority level. 1: usb0 interrupt set to high priority level. bit0: psmb0: smbus (smb0) in terrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value pt3 pcp1 pcp0 ppca0 padc0 pwadc0 pusb0 psmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf6
rev. 1.3 95 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 9.11. eie2: extended interrupt enable 2 sfr definition 9.12. eip2: extended interrupt priority 2 bits7?2: unused. read = 000000 b. write = don?t care. bit1: es1: enable uart1 interrupt. this bit sets the masking of the uart1 interrupt. 0: disable uart1 interrupt. 1: enable uart1 interrupt. bit0: evbus: enable vbus level interrupt. this bit sets the masking of the vbus interrupt. 0: disable all vbus interrupts. 1: enable interrupt requests generated by vbus level sense. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - - es1 evbus 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe7 bits7?2: unused. read = 000000b. write = don?t care. bit1: ps1: uart1 interrupt priority control. this bit sets the priority of the uart1 interrupt. 0: uart1 interrupt set to low priority level. 1: uart1 interrupts set to high priority level. bit0: pvbus: vbus level inte rrupt priority control. this bit sets the priority of the vbus interrupt. 0: vbus interrupt set to low priority level. 1: vbus interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - - ps1 pvbus 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf7
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 96 rev. 1.3 sfr definition 9.13. it01cf: int0/int 1 configuration bit7: in1pl: int1 polarity 0: int1 input is active low. 1: int1 input is active high. bits6?4: in1sl2?0: int1 port pin selection bits these bits select which port pin is assigned to int1 . note that this pin assignment is inde- pendent of the crossbar; int1 will monitor the assigned port pin without disturbing the peripheral that has been assi gned the port pin via the cr ossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). bit3: in0pl: int0 polarity 0: int0 interrupt is active low. 1: int0 interrupt is active high. bits2?0: int0sl2?0: int0 port pin selection bits these bits select which port pin is assigned to int0 . note that this pin assignment is inde- pendent of the crossbar. int0 will monitor the assigned port pin without disturbing the peripheral that has been assi gned the port pin via the cr ossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). r/w r/w r/w r/w r/w r/w r/w r/w reset value in1pl in1sl2 in1sl1 in1sl0 in0pl in0sl2 in0sl1 in0sl0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe4 note: refer to sfr definition 21.1 for int0/1 edge- or leve l-sensitive inte rrupt selection. in1sl2?0 int1 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 in0sl2?0 int0 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7
rev. 1.3 97 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 9.4. power management modes the cip-51 core has two software programmable power management modes: idle and stop. idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all inter - rupts, are inactive, and the internal oscillator is st opped (analog pe ripherals remain in th eir selected states; the external oscillator is not affected). since clocks are running in idle mode, power consumption is depen - dent upon the system clock frequency and the number of p eripherals left in active mode before entering idle. stop mode consumes the least power. figure 1.15 describes the power control register (pcon) used to control the cip-51's power management modes. although the cip-51 has idle and stop modes built in ( as with any standard 8051 architecture), power management of the entire mcu is better accomplished through system clock and individual peripheral management. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw little power when they are not in use. turning off the oscillators lowers power consum ption considerably; however a reset is required to restart the mcu. the internal oscillator can be placed in suspend mode (see section ?14. oscillators? on page 131 ). in suspend mode, the inte rnal oscillator is stopped un til a non-idle usb event is detected, or the vbus input signal matches the polarity selected by the vbpo l bit in register reg0cn ( sfr definition 8.1 ). 9.4.1. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes executio n. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset and thereby termi - nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event o f an inadvertent write to the pcon register. if this behavior is not desired, th e wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro - vides the opportunity for additional power savings, allo w ing the system to remain in the idle mode indefi - nitely, waiting for an external stimulus to wake up the system. refer to section ?11.6. pca watchdog timer reset? on page 103 for more information on the use and configuration of the wdt. 9.4.2. stop mode setting the stop mode select bit (pcon.1) causes the ci p-51 to enter stop mode as soon as the instruc - tion that sets the bit comp letes execution. in s top mo de the internal oscillator, cpu, and all digital peripher - als are stopped; the st ate of the external oscillator circuit is not affected. each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mo de. stop mode can only be terminated by an internal or external reset. on reset, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout of 100 sec.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 98 rev. 1.3 sfr definition 9.14. pcon: power control bits7?2: gf5?gf0: general purpose flags 5?0. these are general purpose flags for use under software control. bit1: stop: stop mode select. setting this bit will place the cip-51 in stop mode. this bit will always be read as 0. 1: cpu goes into stop mode (internal oscillator stopped). bit0: idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clock to cpu, but clock to time rs, interrupts, serial ports, and analog peripherals are still active.) r/w r/w r/w r/w r/w r/w r/w r/w reset value gf5 gf4 gf3 gf2 gf1 gf0 stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x87
rev. 1.3 99 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 10. prefetch engine the 48 mhz versions of the c8051f34x family of device s incorporate a 2-byte prefetch engine. because the access time of the flash memory is 40 ns, and the minimum instruction time is roughly 20 ns, the p refetch engine is necessary for full-speed code exec ution. instructions are re ad from flash memory two bytes at a time by the prefetch engine, and given to the cip-51 processor core to execute. when running linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full speed. when a code branch occurs, the processo r may be stalled for up to two clock cycles while the next set of code bytes is retrieved from flash memory. the flrt bit (flscl.4) determines how many clock cycles are used to read each set of two code bytes from flash. when operating from a system clock of 25 mhz or less, the flrt bit should be set to ?0? so that the prefetch engine takes only one clock cycle for each read. when operating with a system clock of greater than 25 mhz (up to 48 mhz), the flrt b it should be set to ?1?, so that each prefetch code read lasts for two clock cycles. sfr definition 10.1. pfe0cn: prefetch engine control bits 7?6: unused. read = 00b; write = don?t care bit 5: pfen: prefetch enable. this bit enables the prefetch engine. 0: prefetch engine is disabled. 1: prefetch engine is enabled. bits 4?1: unused. read = 0000b; write = don?t care bit 0: flbwe: flash block write enable. this bit allows block writes to flash memory from software. 0: each byte of a software flash write is written individually. 1: flash bytes are written in groups of two. r r r/w r r r r r/w reset value pfen flbwe 00100000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xaf
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 100 rev. 1.3 11. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal d ata memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones ) in open-drain mode. weak pull-ups are enabled dur - ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter - nal oscillator. refer to section ?14. oscillators? on page 131 for information on selecting and configuring the system clock source. the watchdog timer is enabled with the system clock divide d by 12 as its clock source ( section ?22.3. watchdog timer mode? on page 264 details the use of the watchdog timer). program execution begins at location 0x0000. figure 11.1. reset sources pca wdt missing clock detector (one- shot) software reset (swrsf) system reset reset funnel px.x px.x en system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable errant flash operation + - comparator 0 c0rsef rst (wired-or) power on reset + - vdd supply monitor enable '0' internal hf oscillator xtal1 xtal2 external oscillator drive clock multiplier usb controller vbus transition enable internal lf oscillator
rev. 1.3 101 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 11.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . a power-on reset delay (t pordelay ) occurs before the device is released from reset; this delay is typically less than 0.3 ms. figure 11.2 . plots the power-on and v dd monitor reset timing. on exit from a power-on reset, the porsf flag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was t he cause of reset. the content of internal data mem - ory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. software can force a power-on reset by writin g ?1? to the pinrsf bit in register rstsrc. figure 11.2. power-on and v dd monitor reset timing power-on reset vdd monitor reset rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.4 v rst vdd
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 102 rev. 1.3 11.2. power-fail reset / v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 11.2 ). when v dd returns to a level above v rst , the cip-51 will be released from the reset state. note that even though internal data memory contents are not altered by the power-fa il reset, it is impossib le to determine if v dd dropped below the level required for data retention. if the porsf flag reads ?1?, the data may no longer be valid. the v dd monitor is enabled after power-on resets; however its defi ned state (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is enabled and a software reset is performed, the v dd monitor will still be enabled afte r the reset. it is strongly recommended that the v dd monitor be left enabled at all times for any system that contai ns code to write to flash memory. important note: th e v dd monitor must be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabled an d stabilized may cause a s ystem reset. in applica - tions where this reset is undesirable, a de lay can be implemented between enabling the v dd monitor and selecting it as a reset source. the procedure for configuring the v dd monitor as a reset source is shown below: step 1. enable the v dd monitor (vdm0cn.7 = ?1?). step 2. if desired, wait for the v dd monitor to stabilize (see table 11.1 for the v dd monitor turn-on time). step 3. select the v dd monitor as a reset so urce (rstsrc.1 = ?1?). see figure 11.2 for v dd monitor timing. see ta b l e 11.1 for complete electrical charac teristics of the v dd monitor. sfr definition 11.1. vdm0cn: v dd monitor control bit7: vdmen: v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate system resets until it is also selected as a reset source in register rstsrc (sfr definition 11.2). the v dd monitor must be allowed to stabilize before it is selected as a reset source. selecting the v dd monitor as a reset source before it has stabilized will generate a system reset. see table 11.1 for the minimum v dd monitor turn-on time. the v dd monitor is enabled fol- lowing all por resets. 0: v dd monitor disabled. 1: v dd monitor enabled. bit6: v dd stat: v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. bits5?0: reserved. read = variable. write = don?t care. r / wrrrrrrrr e s e t v a l u e vdmen vddstat reserved reserved reserved reserved reserved reserved variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xff
rev. 1.3 103 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 11.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert - ing an active-low signal on the rst pin generates a reset; an external pull-up and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. see ta b l e 11.1 for complete rst pin specifications. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 11.4. missing clock detector reset the missing clock detector (mcd) is a on e-shot circuit that is triggered by the system clock. if more than 100 s pass between rising edges on the system clock, the one-shot will time ou t and generat e a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read ?1?, signifying the mcd as the reset source; otherwise, this bit reads ?0?. writ ing a ?1? to the mcdrsf bit enables the missing clock detector; writing a ?0? disables it. the state of the rst pin is unaffected by this reset. 11.5. comparator0 reset comparator0 can be configured as a reset source by writing a ?1? to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted re set. the comparator0 reset is active-low: if the non-inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0-), a system reset is generated. after a comparator0 reset, the c0rsef flag (rstsr c.5) will read ?1? signi fying comparator0 as the reset source; otherwise, this bit reads ?0?. the state of the rst pin is unaffected by this reset. 11.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as described in section ?22.3. watchdog timer mode? on page 264 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is gen erated and the wdtrsf bit (rstsrc.5) is set to ?1?. the state of the rst pin is unaffected by this reset. 11.7. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code sp ace. this occurs when pswe is set to ?1?, and a movx write operation is attempted above address 0x7fff (32 kb flash devices) or 0xfbff (64 kb fla sh devices). ? a flash read is attempted above user code space. th is occurs when a movc operation is attempted above address 0x7fff (32 kb flash devices) or 0xfbff (64 kb flash devices). ? a program read is attempted above user code spac e. this occu rs when user code attempts to branch to an address above 0x7fff (32 kb flash devices) or 0xfbff (64 kb flash devices). ? a flash read, write or erase attempt is re stricted d ue to a flash security setting (see section ?12.3. security options? on page 109 ). ? a flash write or erase is attempted when the v dd monitor is not enabled. the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 104 rev. 1.3 11.8. software reset software may force a reset by writing a ?1? to the swrsf bit (rstsrc.4). the swrsf bit will read ?1? fol - lowing a software forced reset. the state of the rst pin is unaffected by this reset. 11.9. usb reset writing ?1? to the usbrsf bit in register rstsrc sele cts usb0 as a reset source . with usb0 selected as a reset source, a system reset will be generated when either of the following occur: 1. reset signaling is detected on the usb network. the usb func tion controller (usb0) must be enabled for reset signa ling to be detected. see section ?16. universal serial bus con - troller (usb0)? on page 159 for information on the usb function controller. 2. the voltage on the vbus pin matches the po larity selected by the vbpol bit in register reg0cn. see section ?8. voltage regulator (reg0)? on page 69 for details on the vbus detection circuit. the usbrsf bit will read ?1? followin g a usb reset. the state of the rst pin is unaffected by this reset.
rev. 1.3 105 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 11.2. rstsrc: reset source bit7: usbrsf: usb reset flag 0: read: last reset was not a usb reset; write: usb resets disabled. 1: read: last reset was a usb reset; write: usb resets enabled. bit6: ferror: flash error indicator. 0: source of last reset was not a flash read/write/erase error. 1: source of last reset was a flash read/write/erase error. bit5: c0rsef: comparator0 reset enable and flag. 0: read: source of last reset was not comparator0; write: comparator0 is not a reset source. 1: read: source of last reset was comparator0; write: comparator0 is a reset source (active-low). bit4: swrsf: software reset force and flag. 0: read: source of last reset was not a write to the swrsf bit; write: no effect. 1: read: source of last was a write to the swrsf bit; write: forces a system reset. bit3: wdtrsf: watchdog timer reset flag. 0: source of last reset was not a wdt timeout. 1: source of last reset was a wdt timeout. bit2: mcdrsf: missing clock detector flag. 0: read: source of last reset was not a missing clock detector timeout; write: missing clock detector disabled. 1: read: source of last reset was a missing clock detector timeout; write: missing clock detector enabled; triggers a reset if a missing clock condition is detected. bit1: porsf: power-on / v dd monitor reset flag. this bit is set anytime a power-on reset occu rs. writing this bit selects/deselects the v dd monitor as a reset source. note: writing ?1? to this bit before the v dd monitor is enabled and stabilized can cause a system reset. see register vdm0cn (sfr definition 11.1). 0: read: last reset was not a power-on or v dd monitor reset; write: v dd monitor is not a reset source. 1: read: last reset was a power-on or v dd monitor reset; all other reset flags indeterminate; write: v dd monitor is a reset source. bit0: pinrsf: hw pin reset flag. 0: source of last reset was not rst pin. 1: source of la st reset was rst pin. note: for bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read-modify-write instruct ions read and modify the source enable only. this applies to bits: usbrsf, c0rsef, swrsf, mcdrsf, porsf. r/w r r/w r/w r r/w r/w r reset value usbrsf ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xef
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 106 rev. 1.3 table 11.1. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, v dd = 2.7 to 3.6 v 0.6 v rst input high voltage 0.7 x v dd v rst input low voltage 0.3 x v dd rst input pull-up current rst = 0.0 v 25 40 a v dd por threshold (v rst ) 2.40 2.55 2.70 v missing clock detector tim- eout time from last system clock ris- ing edge to reset initiation 100 220 500 s reset time delay delay between release of any reset source and code execution at location 0x0000 5.0 s minimum rst low time to generate a system reset 15 s v dd monitor turn-on time 100 s v dd monitor supply current 20 50 a
rev. 1.3 107 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 12. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system through the c2 interface or by software using the movx instruction. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automat - ically timed by hardware for proper execution; dat a polling to dete rmine the end of th e write/erase opera - tion is not required. code execution is stalle d during a flash write/erase operation. refer to table 12.1 for complete flash memory el ectrical charac teristics. 12.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial - ized device. for details on the c2 commands to program flash memory, see section ?23. c2 interface? on page 271 . to ensure the integrity of flash contents, it is strongly recommended that the v dd monitor be left enabled in any system which writes or erases flash memory from code. it is also crucial to ensure that the flrt bit in register flscl be set to '1' if a clock speed higher than 25 mhz is being used fo r the device. 12.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. the flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per - formed. the flkey regist er is det ailed in sfr definition 12.2 . 12.1.2. flash erase procedure the flash memory can be programmed by software using the movx write instru ction with the address and data byte to be programmed provided as normal ope rands. before writing to flash memory using movx, flash write operations must be enabled by: (1) writi ng the flash key codes in sequence to the flash lock register (flkey); and (2) setting the pswe program st ore write enable bit (psc tl.0) to logic 1 (this directs the movx writes to target flash memory). the pswe bit remains set until cleared by software. a write to flash memory can clear bits to logic 0 but cann ot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed must be erased before a new value is written. the flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: step 1. disable interrupts (recommended). s tep 2. write the first key code to flkey: 0xa5. step 3. write the second key code to flkey: 0xf1. step 4. set the psee bit (register psctl). step 5. set the pswe bit (register psctl). step 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. step 7. clear the pswe bit (register psctl). step 8. clear the psee bit (register pscti).
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 108 rev. 1.3 12.1.3. flash write procedure bytes in flash memory can be written one byte at a time, or in groups of two. the flbwe bit in register pfe0cn ( sfr definition 10.1 ) controls whether a single byte or a blo ck of two bytes is written to flash during a write operation. when flbwe is cleared to ?0?, the flash will be written one byte at a time. when flbwe is set to ?1?, the flash will be written in two-byte blocks. block writes are performed in the same amount of time as single-byte writes, which can save time when storing large amounts of data to flash memory.during a single-byte write to flash, bytes are written individually, and a flash write will be per - formed after each movx write instruction. the recomme n ded procedure for writing flash in single bytes is: step 1. disable interrupts. s tep 2. clear the flbwe bit (register pfe0cn) to select single-byte write mode. step 3. set the pswe bit (register psctl). step 4. clear the psee bit (register psctl). step 5. write the first key code to flkey: 0xa5. step 6. write the second key code to flkey: 0xf1. step 7. using the movx instruction, write a single data byte to the desired location within the 512-byte sector. step 8. clear the pswe bit. step 9. re-enable interrupts. steps 5-7 must be repeated for each byte to be written. for block flash writes, the flash write procedure is only performed after the last byte of each block is writ - ten with the movx write instruction. a flash write bl o ck is two bytes long, from even addresses to odd addresses. writes must be performed sequentially (i.e . addresses ending in 0b and 1b must be written in order). the flash write will be perform ed following the movx write that target s the address ending in 1b. if a byte in the block does not need to be updated in fl ash, it should be written to 0xff. the recommended procedure for writing flash in blocks is: step 1. disable interrupts. s tep 2. set the flbwe bit (register pfe0cn) to select block write mode. step 3. set the pswe bit (register psctl). step 4. clear the psee bit (register psctl). step 5. write the first key code to flkey: 0xa5. step 6. write the second key code to flkey: 0xf1. step 7. using the movx instruction, write the first data byte to the even block location (ending in 0b). step 8. write the first key code to flkey: 0xa5. step 9. write the second key code to flkey: 0xf1. step 10. using the movx instruction, write the second data byte to the odd block location (ending in 1b). step 11. clear the pswe bit. step 12. re-enable interrupts. steps 5?10 must be repeated for each block to be written.
rev. 1.3 109 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 12.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instructi on. note: movx read instructions always target xram. 12.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft - ware as well as to prevent the viewing of proprietary program code and constants. the program store w rite enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash me mory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, or erases) by unpr otected code or the c2 inte rface. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x 01ff), where n is the 1?s complement number represented by the security lock byte. note that the page containing the flash security lock byte is al so locked when any other flash pages are locked. see example below. table 12.1. flash electrical characteristics parameter conditions min typ max units flash size c8051f340/2/4/6/a/c/d* c8051f341/3/5/7/8/9/b 65536* 32768 bytes bytes endurance 20k 100k erase/write erase cycle time 25 mhz system clock 10 15 20 ms write cycle time 25 mhz system clock 40 55 70 s *note: 1024 bytes at location 0xfc00 to 0xffff are reserved. security lock byte: 11111101b 1?s complement: 00000010b flash pages locked: 3 (2 + flash lock byte page) addresses locked: first two pages of flash: 0x0000 to 0x03ff flash lock byte page: (0xfa00 to 0xfbff for 64k devices; 0x7e00 to 0x7fff for 32k devices)
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 110 rev. 1.3 figure 12.1. flash program me mory map and security byte access limit set according to the flash security lock byte c8051f340/2/4/6/a/c/d 0x0000 0xfbff lock byte reserved 0xfbfe 0xfc00 flash memory organized in 512-byte pages 0xfa00 unlocked flash pages locked when any other flash pages are locked c8051f341/3/5/7/8/9/b 0x0000 0x7fff lock byte 0x7ffe 0x7e00 unlocked flash pages
rev. 1.3 111 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d the level of flash security depends on the flash access method. the three flash access methods that can be restricted are reads, wr ites, and erases from the c2 debug interface, user fi rmware executing on unlocked pages, and user firmware executing on locked pages. accessing flash from the c2 debug interface : 1. any unlocked page may be read, written, or erased. 2. locked pages cannot be read, written, or erased. 3. the page containing the lock byte may be re ad , written, or erased if it is unlocked. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing ?1?s to ?0?s in the lock byte) is not permitted. 6. unlocking flash pages (changing ?0?s to ?1?s in the lock byte) requires the c2 device erase command, which erases all flash pages including the page containing the lock byte and the lock byte itself. 7. the reserved area cannot be read, written, or erased. accessing flash fro m user firmware executing on an unlocked page : 1. any unlocked page except the page containing the l ock byte may be read, written, or erased. 2. locked pages cannot be read, written, or erased. 3. the page containing the lock byte cannot be erased. it may be read or written only if it is un locked. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing ?1?s to ?0?s in the lock byte) is not permitted. 6. unlocking flash pages (changing ?0?s to ?1? s in the lock byte) is not permitted. 7. the reserved area cannot be read, written, or erased. any attempt to access the reserved area, or any other locked page, will re sult in a flash error device reset. accessing flash fro m user firmware executing on a locked page : 1. any unlocked page except the page containing the l ock byte may be read, written, or erased. 2. any locked page except the page containing the lo ck byte may be read, written, or erased. 3. the page containing the lock byte cannot be erased. it may only be read or written. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing ?1?s to ?0?s in the lock byte) is not permitted. 6. unlocking flash pages (changing ?0?s to ?1? s in the lock byte) is not permitted. 7. the reserved area cannot be read, written, or erased. any attempt to access the reserved area, or any other locked page, will re sult in a flash error device reset.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 112 rev. 1.3 sfr definition 12.1. psctl: program store r/w control sfr definition 12.2. flkey: flash lock and key bits7?3: unused: read = 00000b. write = don?t care. bit2: reserved. read = 0b. must write = 0b. bit1: psee: program store erase enable setting this bit (in combination with pswe) a llows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx in struction will erase the entire page that contains the loca- tion addressed by the movx instruction. the va lue of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. bit0: pswe: program store write enable setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx write instruction targets flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - reserved psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8f bits?0: flkey: flash lock and key register write: this register must be writte n to before flash writes or erases can be performed. flash remains locked until this regist er is written to with the following key codes: 0xa5, 0xf1. the timing of the writes does not matter, as long as the codes are written in order. the key codes must be written for each flas h write or erase operation. fl ash will be locked until the next system reset if the wrong codes are written or if a flash operation is attempted before the codes have been written correctly. read: when read, bits 1-0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (w rites/erases allowed). 11: flash writes/erases disa bled until the next reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb7
rev. 1.3 113 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 12.3. flscl: flash scale bits7: fose: flash one-shot enable this bit enables the flash read one-shot. w hen the flash one-shot disabled, the flash sense amps are enabled for a full clock cycle during flash reads. at system clock frequen- cies below 10 mhz, disabling the flash one-s hot will increase system power consumption. 0: flash one-shot disabled. 1: flash one-shot enabled. bits6?5: reserved. read = 00b. must write 00b. bit 4: flrt: flash read time. this bit should be programmed to the smallest allowed value, according to the system clock speed. 0: sysclk <= 25 mhz. 1: sysclk <= 48 mhz. bits3?0: reserved. read = 0000b. must write 0000b. r/w r/w r/w r/w r/w r/w r/w r/w reset value fose reserved reserved flrt reserved reserved reserved reserved 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb6
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 114 rev. 1.3 13. external data memory interface and on-chip xram 4k bytes (c8051f340/2/4/6/a/c/d) or 2k bytes (c8051f341/3/5/7/8/9/b) of ram ar e included on-chip, and mapped into the external data memory space (xram). the 1k bytes of usb fifo space can also be mapped into xram address space for additional genera l-purpose data storage. additionally, an external memory interface (emif) is available on the c8051f340 /1/4/5/8/c device s, which can be used to access off-chip data memories and memory-mapped devices connected to the gpio ports. the external memory space may be accessed using the external move inst ruction (movx) and the data pointer (dptr), or using the movx indirect addressing mode using r0 or r1. if the movx instruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bi t address is provided by the external memory inter - face control register (emi0cn, shown in sfr definition 13.1 ). note: the movx instruction can also be used for writing to the flash memory. see section ?12. flash memory? on page 107 for details. the movx instruction accesses xram by default. 13.1. accessing xram the xram memory space is accessed using the mo vx instruction. the movx instruction has two forms, both of which use an indirect addressing method. th e first method uses the data pointer, dptr, a 16-bit register which contains the effective address of the xram location to be read from or written to. the sec - ond method uses r0 or r1 in combination with the emi0 cn register to generate the effective xram address. examples of both of these methods are given below. 13.1.1. 16-bit movx example the 16-bit form of the movx instructi on accesses the memory location po inted to by the contents of the dptr register. the following series of instructions reads the value of the byte at address 0x1234 into the accumulator a: mov dptr, #1234h ; load dptr with 16-bit address to read (0x1234) movx a, @dptr ; load contents of 0x1234 into accumulator a ? the above example uses the 16-bit immed iate mov instruction to set th e contents of dptr. alternately, the dptr can be accessed through the sfr registers dph, which contains the upper 8-bits of dptr, and dpl, which contains the lower 8-bits of dptr. 13.1.2. 8-bit movx example the 8-bit form of the movx instruction uses the content s of the emi0cn sfr to determine the upper 8-bits of the effective address to be accessed and the contents of r0 or r1 to determine the lower 8-bits of the effective address to be accessed. the following series of instructions read the contents of the byte at address 0x1234 into the accumulator a. mov emi0cn, #12h ; load high byte of address into emi0cn mov r0, #34h ; load low byte of address into r0 (or r1) movx a, @r0 ; load contents of 0x1234 into accumulator a
rev. 1.3 115 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 13.2. accessing usb fifo space the c8051f34x devices include 1k of ra m which functions as usb fifo space. figure 13.1 shows an expanded view of the fifo space and user xram. fifo space is normally accessed via usb fifo regis - ters; see section ?16.5. fifo management? on page 167 for more information on accessing these fifos. the movx instruction should not be used to loa d or modify usb data in the fifo space. unused areas of the usb fifo space may be used a s general purpose xram if necessary. the fifo block operates on the usb clock dom ain; thus the usb clock must be active when accessing fifo space. note that the number of sysclk cycles required by the movx instruction is increased when accessing usb fifo space. to access the fifo ram directly using movx instructio n s, the following conditions must be met: (1) the usbfae bit in register emi0cf must be set to '1', and (2) the usb clock must be greater than or equal to twice the sysclk (usbclk > 2 x sysclk). when this bit is set, the usb fifo space is mapped into xram space at addresses 0x0400 to 0x07ff. the normal xram (on-chip or external) at the same addresses cannot be accessed when the usbfae bit is set to ?1?. important note: the usb clock must be active when accessing fifo space. figure 13.1. usb fifo space and xram me mory map with usbfae set to ?1? on/off-chip xram 0x0000 endpoint0 (64 bytes) free (64 bytes) 0x0400 0x043f 0x0440 0x063f 0x0640 0x073f 0x0740 0x07bf 0x07c0 0x07ff endpoint1 (128 bytes) endpoint2 (256 bytes) endpoint3 (512 bytes) usb fifo space (usb clock domain) 0x03ff on/off-chip xram 0x0800 0xffff
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 116 rev. 1.3 13.3. configuring the external memory interface configuring the external memory interface consists of five steps: 1. configure the output modes of the associated po rt pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins in the crossbar. 2. configure port latches to ?park? the emif pins in a dormant state (usually by setting them to logic ?1?). 3. select multiplexed mode o r non-multiplexed mode. 4. select the memory mode (on-chip only, split mode without bank select, split mode with bank selec t, or off-chip only). 5. set up timing to interface with off-chip memory or peripherals. ? each of these five steps is explained in detail in the following s ections. the po rt selection, multiplexed mode selection, and mode bits are located in the emi0cf register shown in sfr definition 13.2 . 13.4. port configuration the external memory interface appears on ports 4, 3, 2, and 1 when it is used for off-chip memory access. when the emif is used, the crossbar should be co nfigured to skip over the control lines p1.7 ( wr ), p1.6 ( rd ), and if multiplexed mode is se lected p1.3 (ale) using the p1skip register. for more information about configuring the crossbar, see section ?figure 15.1. port i/o functional block diagram (port 0 through port 3)? on page 142 . the external memory interface claims the associated po rt pins for memory oper ations only during the execution of an off-chip movx instruction. once the movx instruction has completed, control of the port pins reverts to the port latches or to the crossbar settings for those pins. see section ?15. port input/ output? on page 142 for more information about the crossbar and port operation and configuration. the port latches should be explicitly configured to ?park? the external memory interface pins in a dor - mant state, most commonly by setting them to a logic 1 . during the execution of the movx instruc tion, the external memory inte rface will explicitly disable the driv - ers on all port pins that are acting as inputs (data[ 7:0] dur ing a read operation , for example). the output mode of the port pins (whether the pin is configured as open-drain or push-pull) is unaffected by the external memory interface operation, and remains cont rolled by the pnmdout registers. in most cases, the output modes of all emif pins should be configured for push-pull mode.
rev. 1.3 117 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 13.1. emi0cn: external memo ry interface control bits7?0: pgsel[7:0]: xr am page select bits. the xram page select bits provide the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. 0x00: 0x0000 to 0x00ff 0x01: 0x0100 to 0x01ff ... 0xfe: 0xfe00 to 0xfeff 0xff: 0xff00 to 0xffff r/w r/w r/w r/w r/w r/w r/w r/w reset value pgsel7 pgsel6 pgsel5 pgsel4 pgsel 3 pgsel2 pgsel1 pgsel0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xaa
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 118 rev. 1.3 sfr definition 13.2. emi0cf: external memory configuration bit7: unused. read = 0b. write = don?t care. bit6: usbfae: usb fifo access enable. 0: usb fifo ram not availabl e through movx instructions. 1: usb fifo ram available using movx instru ctions. the 1k of usb ram will be mapped in xram space at addresses 0x0400 to 0x07ff. the usb clock must be active and greater than or equal to twice the sysclk (usbclk > 2 x sysclk) to access this area with movx instructions. bit5: unused. read = 0b. write = don?t care. bit4: emd2: emif multiplex mode select. 0: emif operates in multiplexed address/data mode. 1: emif operates in non-multiplexed mode (separate address and data pins). bits3?2: emd1?0: emif operating mode select. these bits control the operating mode of the external memory interface. 00: internal only: movx accesses on-chip xr am only. all effective addresses alias to on-chip memory space. 01: split mode without bank select: accesse s below the on-chip xram boundary are directed on-chip. accesses above the on-chip xram boundary are directed off-chip. 8-bit off-chip movx operations use the current contents of the address high port latches to resolve upper address byte. note that in orde r to access off-chip space, emi0cn must be set to a page that is not contained in the on-chip address space. 10: split mode with bank select: accesses below the on-chip xram boundary are directed on-chip. accesses above the on-chip xram boundary are directed off-chip. 8-bit off-chip movx operations use the contents of emi0cn to determine the high-byte of the address. 11: external only: movx accesses off-chip xram only. on-chip xram is not visible to the cpu. bits1?0: eale1?0: ale pulse-width select bi ts (only has effect when emd2 = 0). 00: ale high and ale low pulse width = 1 sysclk cycle. 01: ale high and ale low pulse width = 2 sysclk cycles. 10: ale high and ale low pulse width = 3 sysclk cycles. 11: ale high and ale low pulse width = 4 sysclk cycles. r/w r/w r/w r/w r/w r/w r/w r/w reset value - usbfae - emd2 emd1 emd0 eale1 eale0 00000011 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x85
rev. 1.3 119 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 13.5. multiplexed and non-multiplexed selection the external memory interface is capable of acting in a multiplexe d mode or a non-multiplexed mode, depending on the state of the emd2 (emi0cf.4) bit. 13.5.1. multiplexed configuration in multiplexed mode, the data bus and the lower 8-bits of the address bus share the same port pins: ad[7:0]. in this mode , an external latch (74hc373 or equivalent logic gate) is used to hold the lower 8-bits of the ram address. the external latch is controlled by the ale (address latch enable) signal, which is driven by the external memory interface logic. an example of a multiplexed configuration is shown in figure 13.2 . in multiplexed mode, the external movx operation can b e broken into two phases delineated by the state of the ale signal. during the first phase, ale is high and the lower 8-bits of the address bus are pre - sented to ad[7:0]. during this phase , the address latch is configured such that the ?q? outputs reflect the states of the ?d? inputs. when ale falls, signaling th e beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. later in the second phase, the data bus controls the state of th e ad[7:0] port at the time rd or wr is asserted. see section ?13.7.2. multiplexed mode? on page 127 for more information. figure 13.2. multiplexed configuration example address/data bus address bus e m i f a[15:8] ad[7:0] wr rd ale 64k x 8 sram oe we i/o[7:0] 74hc373 g dq a[15:8] a[7:0] ce v dd 8 (optional)
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 120 rev. 1.3 13.5.2. non-multiplexed configuration in non-multiplexed mode, the data bus and the address bus pins are not shared. an example of a non-multiplexed config uration is shown in figure 13.3 . see section ?13.7.1. non-multiplexed mode? on page 124 for more information about non-multiplexed operation. figure 13.3. non-multiplexed configuration example 13.6. memory mode selection the external data memory space can be configured in one of four modes, shown in figure 13.4 , based on the emif mode bits in the emi0cf register ( sfr definition 13.2 ). these modes are summarized below. more information about the different modes can be found in section ?13.7. timing? on page 122 . figure 13.4. emif operating modes address bus e m i f a[15:0] 64k x 8 sram a[15:0] data bus d[7:0] i/o[7:0] v dd 8 wr rd oe we ce (optional) emi0cf[3:2] = 00 0xffff 0x0000 emi0cf[3:2] = 11 0xffff 0x0000 emi0cf[3:2] = 01 0xffff 0x0000 emi0cf[3:2] = 10 on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram off-chip memory (no bank select) on-chip xram 0xffff 0x0000 off-chip memory (bank select) on-chip xram off-chip memory
rev. 1.3 121 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 13.6.1. internal xram only when emi0cf.[3:2] are set to ?00?, all movx instructions will ta rget the internal xram space on the device. memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries (depending on the ram available on the device). as an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip xram space. ? 8-bit movx operations use the contents of emi0cn to determine the high-byte of the effective address and r0 or r1 to determine the lo w-byte of the effective address. ? 16-bit movx operations use the contents of the 16 -bit dptr to determine the effective address. 13.6.2. split mode without bank select when emi0cf.[3:2] are set to ?01?, the xram memory map is split into two areas, on-chip space and off-chip space. ? effective addresses below the internal xram size boundary will access on-chip xram space. ? effective addresses above the internal xr am size boundary will ac cess off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on-chip or off-chip. however, in the ?no bank select? mode, an 8-bi t movx operation will not drive the upper 8-bits a[15:8] of the address bus during an off-chip access. this allows the user to manipulate the upper address bits at will by setting the port state directly via the port latc hes. this behavior is in contrast with ?split mode with bank select? described below. the lower 8-bits of the address bus a[7:0] are driven, determined by r0 or r1. ? 16-bit movx operations use the contents of dp t r to determine whether the memory access is on-chip or off-chip, and unlike 8-bit movx operations, the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 122 rev. 1.3 13.6.3. split mode with bank select when emi0cf.[3:2] are set to ?10?, the xram memory map is split into two areas, on-chip space and off-chip space. ? effective addresses below the internal xram size boundary will access on-chip xram space. ? effective addresses above the internal xr am size boundary will ac cess off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on-chip or off-chip. the upper 8-bits of the addr ess bus a[15:8] are determined by emi0cn, and the lower 8-bits of the address bus a[7:0] are determined by r0 or r1. all 16-bits of the address bus a[15:0] are driven in ?bank select? mode. ? 16-bit movx operations use the contents of dp t r to determine whether the memory access is on-chip or off-chip, and the full 16-bits of the address bus a[15:0] are driven during the off-chip trans - action. 13.6.4. external only when emi0cf[3:2] are set to ?11?, all movx operations are directed to off-chip space. on-chip xram is not visible to the cpu. this mode is useful for ac cessing off-chip memory located between 0x0000 and the internal xram size boundary. ? 8-bit movx operations ignore the contents of emi0 cn. th e upper address bits a[15:8] are not driven (identical behavior to an off-chip access in ?split mode without bank select? described above). this allows the user to manipulate the upp er address bits at will by setting the port state directly. the lower 8-bits of the effective address a[7:0] are determined by the contents of r0 or r1. ? 16-bit movx operations use the contents of dptr to determine the effective address a[15:0]. the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. 13.7. timing the timing parameters of the external memory inte rface can be configured to enable connection to devices having different setup and hold time requirements. the address setup time, address hold time, rd and wr strobe widths, and in multiple xed mode, the width of the ale pulse are all programmable in units of sysclk periods th rough emi0tc, shown in sfr definition 13.3 , and emi0cf[1:0]. the timing for an off-chip movx instruction can be calculate d by adding 4 sysclk cycles to the timing parameters defined by the emi0tc register. assumi ng non-multiplexed operation, the minimum execution time for an off-chip xram operat ion is 5 sysclk cyc les (1 sysclk for rd or wr pulse + 4 sysclks). for multiplexed operations , the address latch enable signal will re quire a minimum of 2 additional sys - clk cycles. therefore, the minimum exec ution time for an off-chip xram operation in multiplexed mode is 7 sysclk cycles (2 for ale + 1 for rd or wr + 4). the programmable setup and hold times default to the maximum delay settings after a reset. table 13.1 lists the ac parameters for the external memory inter - face, and figure 13.5 through figure 13.10 show the timing diagrams for the different external memory interface modes and movx operations.
rev. 1.3 123 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 13.3. emi0tc: external me mory t iming control bits7?6: eas1?0: emif addr ess setup time bits. 00: address setup time = 0 sysclk cycles. 01: address setup time = 1 sysclk cycle. 10: address setup time = 2 sysclk cycles. 11: address setup time = 3 sysclk cycles. bits5?2: ewr3?0: emif wr and rd pulse-width control bits. 0000: wr and rd pulse width = 1 sysclk cycle. 0001: wr and rd pulse width = 2 sysclk cycles. 0010: wr and rd pulse width = 3 sysclk cycles. 0011: wr and rd pulse width = 4 sysclk cycles. 0100: wr and rd pulse width = 5 sysclk cycles. 0101: wr and rd pulse width = 6 sysclk cycles. 0110: wr and rd pulse width = 7 sysclk cycles. 0111: wr and rd pulse width = 8 sysclk cycles. 1000: wr and rd pulse width = 9 sysclk cycles. 1001: wr and rd pulse width = 10 sysclk cycles. 1010: wr and rd pulse width = 11 sysclk cycles. 1011: wr and rd pulse width = 12 sysclk cycles. 1100: wr and rd pulse width = 13 sysclk cycles. 1101: wr and rd pulse width = 14 sysclk cycles. 1110: wr and rd pulse width = 15 sysclk cycles. 1111:wr and rd pulse width = 16 sysclk cycles. bits1?0: eah1?0: emif address hold time bits. 00: address hold time = 0 sysclk cycles. 01: address hold time = 1 sysclk cycle. 10: address hold time = 2 sysclk cycles. 11: address hold time = 3 sysclk cycles. r/w r/w r/w r/w r/w r/w r/w r/w reset value eas1 eas0 ewr3 ewr2 ewr1 ewr0 eah1 eah0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x84
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 124 rev. 1.3 13.7.1. non-multiplexed mode 13.7.1.1.16-bit movx: emi0cf[4:2] = ?101?, ?110?, or ?111?. figure 13.5. non-multip lexed 16-bit movx timing emif address (8 msbs) from dph emif address (8 lsbs) from dpl p3 p2 p1.7 p1.6 p4 emif write data p3 p2 p1.7 p1.6 p4 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 msbs) from dph emif address (8 lsbs) from dpl p3 p2 p1.6 p1.7 p4 p3 p2 p1.6 p1.7 p4 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 16-bit write nonmuxed 16-bit read
rev. 1.3 125 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 13.7.1.2.8-bit movx without bank select: emi0cf[4:2] = ?101? or ?111?. figure 13.6. non-multip lexed 8-bit movx withou t bank select timing emif address (8 lsbs) from r0 or r1 p3 p2 p1.7 p1.6 p4 emif write data p3 p1.7 p1.6 p4 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 lsbs) from r0 or r1 p3 p2 p1.6 p1.7 p4 p3 p1.6 p1.7 p4 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 8-bit write without bank select nonmuxed 8-bit read without bank select
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 126 rev. 1.3 13.7.1.3.8-bit movx with bank select: emi0cf[4:2] = ?110?. figure 13.7. non-multip lexed 8-bit movx with bank select timing p4 p3 p4 addr[15:8] ad[7:0] p3 p1.7 p1.6 p1.3 p1.7 p1.6 p1.3 t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from emi0cn emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p4 p3 p4 addr[15:8] ad[7:0] p3 p1.6 p1.7 p1.3 p1.6 p1.7 p1.3 t ach t acw t acs ale rd wr emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write with bank select muxed 8-bit read with bank select
rev. 1.3 127 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 13.7.2. multiplexed mode 13.7.2.1.16-bit movx: emi0cf[4:2] = ?001 ?, ?010?, or ?011?. figure 13.8. multiple xed 16-bit movx timing p4 p3 p4 addr[15:8] ad[7:0] p3 p1.7 p1.6 p1.3 p1.7 p1.6 p1.3 t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from dph emif write data emif address (8 lsbs) from dpl t aleh t alel p4 p3 p4 addr[15:8] ad[7:0] p3 p1.6 p1.7 p1.3 p1.6 p1.7 p1.3 t ach t acw t acs ale rd wr emif address (8 msbs) from dph emif address (8 lsbs) from dpl t aleh t alel t rdh t rds emif read data muxed 16-bit write muxed 16-bit read
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 128 rev. 1.3 13.7.2.2.8-bit movx without bank select: emi0cf[4:2] = ?001? or ?011?. figure 13.9. multiplexed 8-bit mo vx without bank select timing p4 p3 p4 addr[15:8] ad[7:0] p1.7 p1.6 p1.3 p1.7 p1.6 p1.3 t ach t wdh t acw t acs t wds ale wr rd emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p4 p3 p4 addr[15:8] ad[7:0] p1.6 p1.7 p1.3 p1.6 p1.7 p1.3 t ach t acw t acs ale rd wr emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write without bank select muxed 8-bit read without bank select
rev. 1.3 129 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 13.7.2.3.8-bit movx with bank select: emi0cf[4:2] = ?010?. figure 13.10. multiplexed 8-bit movx with bank select timing p4 p3 p4 addr[15:8] ad[7:0] p3 p1.7 p1.6 p1.3 p1.7 p1.6 p1.3 t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from emi0cn emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p4 p3 p4 addr[15:8] ad[7:0] p3 p1.6 p1.7 p1.3 p1.6 p1.7 p1.3 t ach t acw t acs ale rd wr emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write with bank select muxed 8-bit read with bank select
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 130 rev. 1.3 table 13.1. ac parameters for exte rnal memory interface parameter description min* max* units t acs address / control setup time 0 3 x t sysclk ns t acw address / control pulse width 1 x t sysclk 16 x t sysclk ns t ach address / control hold time 0 3 x t sysclk ns t aleh address latch enable high time 1 x t sysclk 4 x t sysclk ns t alel address latch enable low time 1 x t sysclk 4 x t sysclk ns t wds write data setup time 1 x t sysclk 19 x t sysclk ns t wdh write data hold time 0 3 x t sysclk ns t rds read data setup time 20 ns t rdh read data hold time 0 ns *note: t sysclk is equal to one period of the device system clock (sysclk).
rev. 1.3 131 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 14. oscillators c8051f34x devices include a programmable internal high-frequency os cillator, a programmable internal low-frequency oscillator (c 8051f340/1/2/3/4/ 5/8/9/a/b/c/d), an external osc illator drive circuit, and a 4x clock multiplier. the internal high -frequency and low-freq uency oscillators can be enabled/disabled and adjusted using the special function registers, as shown in figure 14.1 . the system clock (sysclk) can be derived from either of the in ternal oscillators, the exter nal oscillator circuit, or the 4x clock multiplier divided by 2. the usb clock (usbclk) can be derived from the in ternal oscillator, external oscillator, or 4x clock multiplier. oscillator electrical specifications are given in table 14.1 . figure 14.1. oscillator diagram clock multiplier osc input circuit xtlvld xtal1 xtal2 option 2 vdd xtal2 option 1 10m ? option 3 xtal2 option 4 xtal2 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 clkmul mulen mulinit mulrdy mulsel1 mulsel0 programmable high- frequency oscillator en oscicl oscicn ioscen ifrdy suspend ifcn1 ifcn0 exosc / 2 x 2 x 2 exosc iosc sysclk exosc exosc / 2 exosc / 3 exosc / 4 iosc / 2 usbclk usbclk2-0 clksel usbclk2 usbclk1 usbclk0 clksl2 clksl1 clksl0 iosc programmable low- frequency oscillator (c8051f340/1/2/3/4/5/8/9/ a/b/c/d) en exosc osclcn osclen osclrdy osclf3 osclf2 osclf1 osclf0 oscld1 oscld0 n n osclf3-0
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 132 rev. 1.3 14.1. programmable internal hi gh-frequency (h-f) oscillator all c8051f34x devices include a programmable internal oscillator that defaults as the system clock after a system reset. the in ternal oscillator period ca n be programmed via the os cicl register shown in sfr definition 14.2 . the oscicl register is factory calibrated to obtain a 12 mhz internal oscillator frequency. electrical specifications for the prec ision internal oscillator are given in table 14.1 on page 141 . note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the ifcn bits in register oscicn. the divide value defaults to 8 following a reset. 14.1.1. internal h-f oscillator suspend mode the internal high-fre quency oscillator may be placed in suspend mode by writing ?1? to the suspend bit in register oscicn. in suspend mode, the internal h-f oscillator is stopped until a non- idle usb event is detected ( section 16 ) or vbus matches the polarity selected by the vbpol bit in register reg0cn ( sec - tion 8.2 ). note that the usb transc eiver can still detect usb ev ents when it is disabled. sfr definition 14.1. oscicn: internal h-f oscillator control bit7: ioscen: internal h- f oscillator enable bit. 0: internal h-f oscillator disabled. 1: internal h-f oscillator enabled. bit6: ifrdy: internal h-f osc illator frequ ency ready flag. 0: internal h-f oscillator is no t running at prog rammed fr equency. 1: internal h-f oscillator is running at prog rammed fr equency. bit5: suspend: force suspend writing a ?1? to this bit will forc e the internal h-f oscillator to be stopped. the oscillator will be re-started on the next non-idle usb event (i .e., resume signaling) or vbus interrupt event (see sfr definition 8.1). bits4?2: unused. read = 000b, write = don't care. bits1?0: ifcn1?0: internal h-f oscillator frequ ency control. 00: sysclk derived from internal h-f oscillator divided by 8. 01: sysclk derived from internal h-f oscillator divided by 4. 10: sysclk derived from internal h-f oscillator divided by 2. 11: sysclk derived from inter nal h-f oscillator divided by 1. r/w r r/w r r/w r/w r/w r/w reset value ioscen ifrdy suspend - - - ifcn1 ifcn0 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb2
rev. 1.3 133 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 14.2. oscicl: internal h-f oscillator calibration 14.2. programmable internal low -frequency (l-f) oscillator the c8051f340/1/2/3/4/5/8/9/c/d devices include a prog rammable internal oscillator which operates at a nominal frequency of 80 khz. the low-freq uency oscillator circuit includes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the oscld bits in the osclcn register (see sfr definition 14.3 ). additionally, the osclf bits (osclcn5:2) can be used to adjust the oscilla tor?s output frequency. 14.2.1. calibrating the internal l-f oscillator timers 2 and 3 inclu de capture functions that can be used to capture the oscillator frequency, when run - ning from a known time base. when either timer 2 or t imer 3 is configured for l-f oscillator capture mode, a falling edge (timer 2) or rising edge (timer 3) of the low-frequency osc illator?s output will cause a capture event on the corresponding timer. as a capture event occurs, the current timer value (tmrnh:tmrnl) is copied into the timer reload re gisters (tmrnrlh:tmrnrll). by recording the differ - ence between two successive time r capture values, the lo w-frequency oscillator?s period can be calcu - lated. the osclf bits can th en be adjusted to produce the desired osc illator period. bits4?0: osccal: oscilla tor calibration value these bits determine t he internal h-f oscillator period. when set to 00000b, the oscillator operates at its fastest setting. when set to 11111b, the oscillato r operates at is slowest set- ting. the contents of th is register are factory calibrated to pr oduce a 12 mhz internal oscilla- tor frequency. note: the contents of this register are undefined when clock recovery is enabled. see section ?16.4. usb clock configuration? on page 166 for details on clock recovery. r/w r/w r/w r/w r/w r/w r/w r/w reset value --- osccal variable bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xb3
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 134 rev. 1.3 sfr definition 14.3. osclcn: internal l-f oscillator control bit7: osclen: internal l-f oscillator enable. 0: internal l-f oscillator disabled. 1: internal l-f oscillator enabled. bit6: osclrdy: internal l-f oscillator ready flag. 0: internal l-f oscillato r frequency not stabilized. 1: internal l-f oscilla tor frequency stabilized. bits5?2: osclf[3:0]: internal l-f oscillator frequen cy control bits. fine-tune control bi ts for the internal l-f oscillator frequency. when set to 0000b, the l-f oscillator operates at its fastest setting. when set to 1111b, the l-f oscillator operates at its slowest setting. bits1?0: oscld[1:0]: internal l-f oscillator divider select. 00: divide by 8 selected. 01: divide by 4selected. 10: divide by 2 selected. 11: divide by 1 selected. r/w r r/w r r/w r/w r/w r/w reset value osclen osclrdy osclf3 osclf2 osclf1 osclf0 oscld1 oscld0 00vvvv00 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x86
rev. 1.3 135 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 14.3. external oscill ator drive circuit the external oscillator circuit may driv e an external crystal, ce ramic resonator, capacito r, or rc network. a cmos clock may also provide a clock input. for a crys tal or ceramic resonator configuration, the crystal/ resonator must be wired across the xtal1 and xtal2 pins as shown in option 1 of figure 14.1 . a 10 m ?? resistor also must be wired across the xtal1 and xt al2 pins for the crystal/resonator configuration. in rc, capacitor, or cmos clock configuration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 14.1 . the type of external os cillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see sfr definition 14.4 ) important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive circ uit is enabled in crystal/r esonator mode , port pins p0.6 and p0.7 (c8051f340 /1/4/5/8) or p0.2 and p0 .3 (c8051f342/3/6/7/9/a/b) are used as xtal1 and xtal2 respectively. when the external oscillator drive circuit is enabled in capa citor, rc, or cmos clock mode, port pin p0.7 (c8051f340/1/4/5/8) or p0.3 (c805 1f342/3/6/7/9/a/b) is used as xtal2. the port i/ o crossbar should be configured to skip the port pins used by the osc illator circuit; see section ?15.1. priority crossbar decoder? on page 144 for crossbar configuration. additionally, when using the external oscillator circuit in cryst al/resonator , capacitor, or rc mode, the a ssociated port pins should be configured as analog inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?15.2. port i/o initialization? on page 147 for details on port input mode selection. 14.3.1. clocking timers directly through the external oscillator the external oscillato r source divided by eight is a clock option for the timers ( section ?21. timers? on page 235 ) and the programmable counter array (pca) ( section ?22. programmable counter array (pca0)? on page 255 ). when the external oscillator is used to clock these peri pherals, but is not used as the system clock, the external o scillator frequency must be less than or equal to the system clock fre - quency. in this configuration, the clock supplied to the perip heral (external oscillator / 8) is synchronized with the system clock; the jitter associated with this synchronization is limited to 0.5 system clock cycles. 14.3.2. external crystal example if a crystal or ceramic resonator is used as an external osc illator source for the mcu, the circuit should be configured as shown in figure 14.1 , option 1. the external oscillato r frequency contro l value (xfcn) should be chosen from the crystal column of the table in sfr definition 14.4 (oscxcn register). for example, a 12 mhz crystal requires an xfcn setting of 111b. when the crystal oscillator is first enabled, the oscillato r amplitude detection circui t requires a settling time to achieve proper bias. introducing a delay of 1 ms between enabling the o scillator and checking the xtl vld bit will prevent a premature sw itch to the external oscillator as the system clock. switching to the external oscillator before the crysta l oscillator has stabilized can result in unpredictable behavior. the rec - ommended procedure is: step 1. enable the external oscillator. s tep 2. wait at least 1 ms. step 3. poll for xtlvld => ?1?. step 4. switch the system cl ock to the external oscillator. important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces which could introduce noise or interference.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 136 rev. 1.3 14.3.3. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 14.1 , option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter - mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscillation. if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: referring to the table in sfr definition 14.4 , the required xfcn setting is 010b. programming xfcn to a higher setting in rc mo de w ill improve frequency accuracy at an increased external oscillato r supply cur- rent. 14.3.4. external capacitor example if a capacitor is used as an external oscillator for the mcu, the circuit should be configured as shown in figure 14.1 , option 3. the capacitor should be no greater than 100 pf; however for very small cap acitors, the total capacitance may be dominated by parasiti c ca pacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci - tor to be used and find the frequency of oscilla tion from the equati ons below. assume v dd = 3.0 v and c = 50 pf: if a frequency of roughly 150 khz is desired, select the k fa ctor from the table in sfr definition 14.4 as kf = 22: therefore, the xfcn value to use in this example is 011b. f 1.23 10 3 ?? rc ----------------------- - 1.23 10 3 ?? 246 50 ? ?? ------------- ------------ - 0.1 mhz 100 khz == == f kf cv dd ? ?? -------------- ----------- kf 50 x 3 ?? mhz -------------------------------- == f kf 150 mhz ---------------------- = f 22 150 -------- - 0.146 mhz, or 146 khz ==
rev. 1.3 137 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 14.4. oscxcn: external oscillator control bit7: xtlvld: crystal oscillator valid flag. (read only when xoscmd = 11x.) 0: crystal oscillator is unused or not yet stable. 1: crystal oscillator is running and stable. bits6?4: xoscmd2?0: extern al oscillator mode bits. 00x: external osc illator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. bit3: reserved. read = 0, write = don't care. bits2?0: xfcn2?0: external osc illator frequency control bits. 000-111: see table below: crystal mode (circuit from figure 14.1, option 1; xoscmd = 11x) choose xfcn value to match crystal or resonator frequency. rc mode (circuit from figure 14.1, option 2; xoscmd = 10x) choose xfcn value to match frequency range: f = 1.23(10 3 ) / (r x c) , where f = frequency of clock in mhz c = capacitor value in pf r = pull-up resist or value in k ? c mode (circuit from figure 14.1, option 3; xoscmd = 10x) choose k factor (kf) for the oscillati on frequency desired: f = kf / (c x v dd ) , where f = frequency of clock in mhz c = capacitor value the xtal2 pin in pf v dd = power supply on mcu in volts r r/w r/w r/w r r/w r/w r/w reset value xtlvld xoscmd2 xoscmd1 xoscmd 0 - xfcn2 xfcn1 xfcn0 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xb1 xfcn crystal (xoscmd = 11x) rc (xoscmd = 10x) c (xoscmd = 10x) 000 f ? 32 khz f ?? 25 khz k factor = 0.87 001 32 khz ?? f ?? 84khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 84 khz ? f ?? 225 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 225 khz ? f ?? 590 khz 100 khz ?? f ?? 200 khz k factor = 22 100 590 khz ? f ?? 1.5 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.5 mhz ? f ?? 4 mhz 400 khz ?? f ?? 800 khz k factor = 180 110 4 mhz ? f ?? 10 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 10 mhz ? f ?? 30 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 138 rev. 1.3 14.4. 4x clock multiplier the 4x clock multiplier allows a 12 mhz oscillator to generate the 48 mhz clock required for full speed usb com munication (see section ?16.4. usb clock configuration? on page 166 ). a divided version of the multiplier output can also be used as the system clock. c8051f340/1/ 2/3 devices can use the 48 mhz clock multiplier output as system clock. see ta b l e 3.1, ?global dc electrical characteristics,? on page 25 for system clock frequency specifications. see section 14.5 for details on system clock and usb clock source selection. the 4x clock multiplier is configured via the clkmul register. the procedure for configuring and enabling th e 4x clock multip lier is as follows: 1. reset the multiplie r by writing 0x00 to register clkmul. 2. select the multiplier input source via the mulsel bits. 3. enable the multiplier with the mulen bit (clkmul | = 0x80). 4. delay for >5 s. 5. initialize the multip lier with the mulinit bit (clkmul | = 0xc0). 6. poll for mulrdy => ?1?. important note: when using an external oscillator as the input to the 4x clock multiplier, the exter - nal source must be enabled and stable be fo re the multiplier is initialized. see section 14.5 for details on selecting an external oscillator source. sfr definition 14.5. clkmul: clock multiplier control bit7: mulen: clock multiplier enable 0: clock multiplier disabled. 1: clock multiplier enabled. bit6: mulinit: clock multiplier initialize this bit should be a ?0? when the clock multiplie r is enabled. once enabled, writing a ?1? to this bit will initialize the clock multiplier. the mulrdy bit reads ?1? w hen the clock multiplier is stabilized. bit5: mulrdy: clock multiplier ready this read-only bit indicates the status of the clock multiplier. 0: clock multiplier not ready. 1: clock multiplier ready (locked). bits4?2: unused. read = 000b; write = don?t care. bits1?0: mulsel: clock multiplier input select these bits select the clock supplied to the clock multiplier. r/w r/w r r/w r/w r/w r/w r/w reset value mulen mulinit mulrdy - - - mulsel 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address 0xb9 mulsel selected clock 00 internal oscillator 01 external oscillator 10 external oscillator / 2 11 reserved
rev. 1.3 139 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 14.5. system and us b clock selection the internal oscillator requires littl e start-up time and may be selected as the syst em or usb clock immedi - ately following the oscicn write that enables the inte rn al oscillator. external crystals and ceramic resona - tors typically require a start-up time before they are settled and ready for use. the crystal valid flag (xtl vld in register oscxcn) is set to ?1? by hardware when the external oscillator is settled. to avoid reading a false xtlvld, in crystal mode software should delay at least 1 ms between enabling the e xternal oscillator and checking xtlvld. rc and c modes typically require no startup time. 14.5.1. system clock selection the clksl[1:0] bits in register cl ksel select which osc illator source is used as the system clock. clksl[1:0] must be set to 01b for the system clock to run from the external oscillato r; however the exter - nal oscillator may still clock certain pe ripherals (timers, pca , usb) when the internal oscillator is selected as the system clock. the sy stem clock may be switched on-the-fly be tween the internal o scillator, external oscillator, and 4x clock multiplier so long as the selected oscillator is enabled and has settled. c8051f340/ 1/2/3 devices can use the 48 mhz clock multiplier output as system clock. see ta b l e 3.1, ?global dc elec - trical characteristics,? on page 25 for system clock frequency specifications. when operating with a sys - tem clock of greater than 25 mhz (up to 48 mhz), the flrt bit (flscl.4) should be set to ?1?. see section ?10. prefetch engine? on page 99 for more details. 14.5.2. usb clock selection the usbclk[2:0] bits in register cl ksel select which oscillator source is used as the usb clock. the usb clock may be derived from the 4x clock multiplier output, a divided vers ion of the internal oscillator, or a divided version of the exte rnal oscillator. note that the usb clock must be 48 mhz when operating usb0 as a full speed function; the usb clock must be 6 mhz when operating usb0 as a low speed function. see sfr definition 14.6 for usb clock selection options. some example usb clock configurations for full and low speed mode are given below: internal oscillator clock signal input source selection register bit settings usb clock clock multiplier usbclk = 000b clock multiplier input inter nal oscillator* mulsel = 00b internal oscillator divide by 1 ifcn = 11b external oscillator clock signal input source selection register bit settings usb clock clock multiplier usbclk = 000b clock multiplier input exter nal oscillator mulsel = 01b external oscillator crystal oscillator mode 12 mhz crystal xoscmd = 110b xfcn = 111b *note: clock recovery must be enabled for this configuration. internal oscillator clock signal input source selection register bit settings usb clock internal osc illator / 2 usbclk = 001b internal oscillator divide by 1 ifcn = 11b external oscillator clock signal input source selection register bit settings
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 140 rev. 1.3 sfr definition 14.6. clksel: clock select usb clock external osc illator / 4 usbclk = 101b external oscillator crystal oscillator mode 24 mhz crystal xoscmd = 110b xfcn = 111b internal oscillator clock signal input source selection register bit settings bit 7: unused. read = 0b; write = don?t care. bits6?4: usbclk2?0: usb clock select these bits select the clock supplied to usb0. when operating usb0 in full-speed mode, the selected clock should be 48 mhz. when operating usb0 in low-speed mode, the selected clock should be 6 mhz. bit3: unused. read = 0b; write = don?t care. bits2?0: clksl2?0: system clock select these bits select the system clock source. wh en operating from a system clock of 25 mhz or less, the flrt bit should be set to ?0?. when operating with a system clock of greater than 25 mhz (up to 48 mhz), the flrt bit (flscl.4) should be set to ?1?. see section ?10. prefetch engine? on page 99 for more details. r/w r/w r/w r/w r/w r/w r/w r/w reset value - usbclk - clksl 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address 0xa9 usbclk selected clock 000 4x clock multiplier 001 internal oscillator / 2 010 external oscillator 011 external oscillator / 2 100 external oscillator / 3 101 external oscillator / 4 110 reserved 111 reserved clksl selected clock 000 internal oscillator (a s determined by the ifcn bits in register oscicn) 001 external oscillator 010 4x clock multiplier / 2 011* 4x clock multiplier* 100 low-frequency oscillator 101-111 reserved *note: this option is only available on 48 mhz devices.
rev. 1.3 141 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d table 14.1. oscillator electrical characteristics v dd = 2.7 to 3.6 v; ?40 to +85 c unless otherwise specified parameter conditions min typ max units internal high-frequency oscillator (u si ng factory-calibrated settings) oscillator frequency ifcn = 11b 11.82 12.00 12.18 mhz oscillator supply current ? (from v dd ) 24 oc, v dd = 3.0 v, oscicn.7 = 1 ?685? a internal low-frequency oscillator (using factory-calibrated settings) oscillator frequency oscld = 11b 72 80 99 khz oscillator supply current ? (from v dd ) 24 oc, v dd = 3.0 v, osclcn.7 = 1 ?7.0? a external usb clock requirements usb clock frequency* full speed mode low speed mode 47.88 5.91 48 6 48.12 6.09 mhz *note: applies only to extern al oscillator sources.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 142 rev. 1.3 15. port input/output digital and analog resources are available through 40 i/o pins (48-pin packages) or 25 i/o pins (32-pin packages). port pins are organized as shown in figure 15.1 . each of the port pins can be defined as gen - eral-purpose i/o (gpio) or analog input; port pins p0 .0 -p3.7 can be assigned to one of the internal digital resources as shown in figure 15.3 . the designer has complete control over which functions are assigned, limited only by the number of physic al i/o pins. this resource assignment flexibility is achi eved through the use of a priority crossbar decoder. note that the stat e of a port i/o pin can always be read in the corre - sponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital reso u rces to the i/o pins based on the priority decoder ( figure 15.3 and figure 15.4 ). the registers xbr0, xbr 1, and xbr2 defined in sfr definition 15.1 , sfr definition 15.2 , and sfr definition 15.3 , are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 15.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port outp u t mode registers (pnmdout, where n = 0,1,2,3,4). com - plete electrical specifications for port i/o are given in ta b l e 15.1 on page 158 . figure 15.1. port i/o fun ctional block diagram (port 0 through port 3) xbr0, xbr1, xbr2, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 pnmdout, pnmdin registers uart0 (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 6 pca cp1 outputs 2 4 spi cp0 outputs 2 p1 i/o cells p1.0 p1.7 8 p2 i/o cells p2.0 p2.7 8 p3 i/o cells p3.0 8 (port latches) p0 8 8 8 8 p1 p2 p3 *p3.1-p3.7 only available on 48-pin packages **uart1 only available on c8051f340/1/4/5/8/a/b devices uart1** 2 p3.7* (p0.0-p0.7) (p1.0-p1.7) (p2.0-p2.7) (p3.0-p3.7*)
rev. 1.3 143 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 15.2. port i/o cell block diagram gnd port-outenable port-output push-pull vdd vdd weak-pullup (weak) port pad analog input analog select port-input
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 144 rev. 1.3 15.1. priority crossbar decoder the priority cro ssbar decoder ( figure 15.3 ) assigns a priority to each i/o f unction , starting at the top with uart0. when a digital resource is selected, the leas t- significant unassigned port pin is assigned to that resource (excluding uart0, which is always at pins 4 and 5). if a port pin is assigned, the crossbar skips that pin when assigning the next se lected resource. additi onally, the crossbar will skip port pins whose associated bits in the pnskip registers are set. the pn skip registers allow software to skip port pins that are to be used for analog input, dedicated functions, or gpio. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corres ponding pnskip bit should be se t. this applies to the vref signal, external oscillator pins (xtal1, xtal2), the adc?s external conversion st art signal (cnvstr), emif control signals, and any selected adc or comparator inputs. the pnskip registers may also be used to skip pins to be used as gpio. the crossbar skips selected pins as if they were already assigned, and moves to the next unas - signed pin. figure 15.3 shows all the possible pins available to each peripheral. figure 15.4 shows the crossbar decoder priority with no port pins skippe d. f igure 15.5 shows a crossbar example with pins p0.2, p0.3, and p1.0 skipped. figure 15.3. peripheral ava ilability on port i/o pins xtal1 xtal2 cnvstr vref xtal1 xtal2 ale cnvstr vref rd wr 01234567012345670123456701234567 sck miso mosi nss* cp0 cp0a cp1 t1 tx1** **uart1 available only on c8051f340/1/4/5/8/a/b devices *nss is only pinned out in 4-wire spi mode cex3 cex4 p1 cp1a cex2 cex0 cex1 sysclk rx0 sda p3 sf signals (48-pin package) p3.1-p3.7 unavailable on the 32-pin packages p2 scl p0 sf signals (32-pin package) pin i/o tx0 special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially available to peripheral sf signals eci t0 rx1**
rev. 1.3 145 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 15.4. crossbar priority decoder in example configuration (no pins skipped) xtal1 xtal2 cnvstr vref xtal1 xtal2 ale cnvstr vref rd wr 01234567012345670123456701234567 sck miso mosi nss* *nss is only pinned out in 4-wire spi mode cp0 cp0a cp1 t1 tx1** **uart1 available only on c8051f340/1/4/5/8/a/b devices 00000000000000000000000000000000 example: xbr0 = 0x07 xbr1 = 0x43 p3 p3skip[0:7] sf signals (48-pin package) p3.1-p3.7 unavailable on the 32-pin packages p2 cex3 cex4 p1skip[0:7] p1 cp1a cex2 cex0 cex1 sysclk rx0 sda scl p0 sf signals (32-pin package) pin i/o tx0 eci t0 rx1** p2skip[0:7] special function signals are not assigned by the crossbar. when these signals are sf signals p0skip[0:7] port pin assigned to peripheral by the crossbar
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 146 rev. 1.3 figure 15.5. crossbar priori ty decoder in example conf iguration (3 pins skipped) registers xbr0, xbr1, and xbr2 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the cro ssbar assigns both pins associated with the smbus (sda and scl); when either uart is selected, the cr ossbar assigns both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for boot loading purposes: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standard port i/os appear contiguously after the prioritized functions have been assigned. important note: the spi can be operated in either 3-wire or 4-wire modes, depending on the state of the nssmd1-nssmd0 bits in register spi 0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. xtal1 xtal2 cnvstr vref xtal1 xtal2 ale cnvstr vref rd wr 01234567012345670123456701234567 sck miso mosi nss* *nss is only pinned out in 4-wire spi mode cp0 cp0a cp1 t1 tx1** **uart1 available only on c8051f340/1/4/5/8/a/b devices 00110000100000000000000000000000 example: xbr0 = 0x07 xbr1 = 0x43 p0skip = 0x0c p1skip = 0x01 sda scl port pin assigned to peripheral by the crossbar cp1a cex3 cex4 cex2 cex0 cex1 sysclk p0 p1 special function signals are not assigned by the crossbar. w hen these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. p0skip[0:7] p1skip[0:7] p2 sf signals eci t0 rx1** p3 p3.1-p3.7 unavailable on the 32-pin pa cka ge s sf signals (48-pin package) p2skip[0:7] p3skip[0:7] sf signals (32-pin package) pin i/o tx0 rx0
rev. 1.3 147 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 15.2. port i/o initialization port i/o initialization consis ts of the following steps: step 1. select the input mode (analog or digital) for all port pins, using the port input mode r egister (pnmdin). step 2. select the output mode (open-drain or push -pull) for all port pins, using the port output mode register (pnmdout). step 3. select any pins to be skipped by the i/o crossbar using the port skip registers (pnskip). step 4. assign port pins to desired peripherals (xbr0, xbr1). step 5. enable the cr ossbar (xbare = ?1?). all port pins must be configured as either analog or dig ital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver are disabled. this process saves power and reduces noise on the analog inpu t. pins configured as digita l inputs may still be used by an alog peripherals ; however this practice is not recommended. to configure a port pin fo r digital input, write ?0? to the corresponding bit in register pnmdout, and write ?1? to the corresponding port latch (register pn). additionally, all analog input pins should be configur ed to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a ?1? indicates a digital input, and a ?0? indicates an analog input. all pins default to digital inputs on reset. the output driver characteristics of the i/o pins ar e d efined using the port output mode registers (pnmd - out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bi t in xbr1 is ?0?, a we ak pull-up is enabled for all port i/o con - figured as open-drain. weakpud does not affect the pu sh- pull port i/o. furthermore, the weak pull-up is turned off on an output that is driving a ?0? to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the appr o priate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to ?1? enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out using the priority decode table; as an alternative, the confi guration wizard utility of the silicon labs ide software will determine the port i/o pin-assignments based on the xbrn register settings. important note: the crossbar must be enabled to use ports p0, p1, p2, and p3 as standard port i/o in output mode. these port output drivers are disabled while the crossbar is disabled. port 4 always func - tions as standard gpio.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 148 rev. 1.3 sfr definition 15.1. xbr0: port i/o cro ssb ar register 0 bit7: cp1ae: comparator1 asynchronous output enable 0: asynchronous cp1 unavailable at port pin. 1: asynchronous cp1 routed to port pin. bit6: cp1e: comparator1 output enable 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. bit5: cp0ae: comparator0 asynchronous output enable 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. bit4: cp0e: comparator0 output enable 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. bit3: syscke: /sysclk output enable 0: /sysclk unavaila ble at port pin. 1: /sysclk output r outed to port pin. bit2: smb0e: smbus i/o enable 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. bit1: spi0e: spi i/o enable 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. bit0: urt0e: uart0 i/o output enable 0: uart0 i/o unavailable at port pins. 1: uart0 tx0, rx0 routed to port pins p0.4 and p0.5. r/w r/w r/w r/w r/w r/w r/w r/w reset value cp1ae cp1e cp0ae cp0e syscke smb0e spi0e urt0e 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xe1
rev. 1.3 149 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 15.2. xbr1: port i/o cro ssb ar register 1 sfr definition 15.3. xbr2: port i/o cro ssb ar register 2 bit7: weakpud: port i/o weak pull-up disable. 0: weak pull-ups enabled (except for ports whose i/o are configured as analog input or push-pull output). 1: weak pull-ups disabled. bit6: xbare: cros sbar enable. 0: crossbar disabled; all port drivers disabled. 1: crossbar enabled. bit5: t1e: t1 enable 0: t1 unavailable at port pin. 1: t1 routed to port pin. bit4: t0e: t0 enable 0: t0 unavailable at port pin. 1: t0 routed to port pin. bit3: ecie: pca0 exter nal counter input enable 0: eci unavailable at port pin. 1: eci routed to port pin. bits2?0: pca0me: pca module i/o enable bits. 000: all pca i/o unavailable at port pins. 001: cex0 routed to port pin. 010: cex0, cex1 routed to port pins. 011: cex0, cex1, cex2 routed to port pins. 100: cex0, cex1, cex2, cex3 routed to port pins. 101: cex0, cex1, cex2, cex3, cex4 routed to port pins. 110: reserved. 111: reserved. r/w r/w r/w r/w r/w r/w r/w r/w reset value weakpud xbare t1e t0e ecie pca0me 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe2 bits7?1: reserved: always write to 0000000b bit0: urt1e: uart1 i/o output enable (c8051f340/1/4/5/8/a/b only) 0: uart1 i/o unavailable at port pins. 1: uart1 tx1, rx1 routed to port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value urt1e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe3
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 150 rev. 1.3 15.3. general purpose port i/o port pins that remain unassigned by the crossbar and are not used by analog peripherals can be used for general purpose i/o. ports 3-0 are accessed through corresponding special function registers (sfrs) that are both byte addressable and bit addressable. po rt 4 (48-pin packages only) uses an sfr which is byte-addressable. when writing to a port, the value wr itten to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port i/o pin). the except ion to this is the executio n of the read-modify-write instructions. the read-mod ify-write instructions wh en operating on a port sfr are the following: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an individual bit in a port sfr. for these instructions, the value of the register (not the pin) is read, modified, and written back to the sfr. sfr definition 15.4. p0: port0 latch sfr definition 15.5. p0mdin: port0 input mode bits7?0: p0.[7:0] write - output appears on i/o pins per crossbar re gisters (when xbare = ?1?). 0: logic low output. 1: logic high output (high impedance if corresponding p0mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p0mdin. directly reads port pin when configured as digital input. 0: p0.n pin is logic low. 1: p0.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: (bit addressable) 0x80 bits7?0: analog input configuration bits for p0.7?p0.0 (respectively). port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is configured as an analog input. 1: corresponding p0.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xf1
rev. 1.3 151 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 15.6. p0mdout: port0 output mode sfr definition 15.7. p0skip: port0 skip bits7?0: output configuration bits for p0.7?p0.0 (res pectively): ignored if corresponding bit in regis- ter p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. (note: when sda and scl appear on any of the port i/o, each are open-drain regardless of the value of p0mdout). r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xa4 bits7?0: p0skip[7:0]: port0 cr ossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd4
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 152 rev. 1.3 sfr definition 15.8. p1: port1 latch sfr definition 15.9. p1mdin: port1 input mode sfr definition 15.10. p1mdout: port1 output mode bits7?0: p1.[7:0] write - output appears on i/o pins per crossbar re gisters (when xbare = ?1?). 0: logic low output. 1: logic high output (high impedance if corresponding p1mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p1mdin. directly reads port pin when configured as digital input. 0: p1.n pin is logic low. 1: p1.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x90 bits7?0: analog input configuration bits for p1.7?p1.0 (respectively). port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is configured as an analog input. 1: corresponding p1.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf2 bits7?0: output configuration bits for p1.7?p1.0 (res pectively): ignored if corresponding bit in regis- ter p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa5
rev. 1.3 153 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 15.11. p1skip: port1 skip sfr definition 15.12. p2: port2 latch sfr definition 15.13. p2mdin: port2 input mode bits7?0: p1skip[7:0]: port1 cr ossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xd5 bits7?0: p2.[7:0] write - output appears on i/o pins per crossbar re gisters (when xbare = ?1?). 0: logic low output. 1: logic high output (high impedance if corresponding p2mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p2mdin. directly reads port pin when configured as digital input. 0: p2.n pin is logic low. 1: p2.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa0 bits7-0: analog input configuration bits for p2.7-p2.0 (respectively). port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p2.n pin is configured as an analog input. 1: corresponding p2.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf3
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 154 rev. 1.3 sfr definition 15.14. p2mdout: port2 output mode sfr definition 15.15. p2skip: port2 skip bits7?0: output configuration bits for p2.7?p2.0 (res pectively): ignored if corresponding bit in regis- ter p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xa6 bits7?0: p2skip[7:0]: port2 cr ossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xd6
rev. 1.3 155 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 15.16. p3: port3 latch sfr definition 15.17. p3mdin: port3 input mode sfr definition 15.18. p3mdout: port3 output mode bits7?0: p3.[7:0] write - output appears on i/o pins. 0: logic low output. 1: logic high output (high impedance if corresponding p3mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p3mdin. directly reads port pin when configured as digital input. 0: p3.n pin is logic low. 1: p3.n pin is logic high. note: p3.1?3.7 are only available on 48-pin devices. r/w r/w r/w r/w r/w r/w r/w r/w reset value p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb0 bits7?0: analog input configuration bits for p3.7?p3.0 (respectively). port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p3.n pin is configured as an analog input. 1: corresponding p3.n pin is not configured as an analog input. note: p3.1?3.7 are only available on 48-pin devices. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xf4 bits7?0: output configuration bits for p3.7?p3.0 (res pectively); ignored if corresponding bit in regis- ter p3mdin is logic 0. 0: corresponding p3.n output is open-drain. 1: corresponding p3.n output is push-pull. note: p3.1?3.7 are only available on 48-pin devices. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xa7
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 156 rev. 1.3 sfr definition 15.19. p3skip: port3 skip sfr definition 15.20. p4: port4 latch bits7?0: p3skip[3:0]: port3 cr ossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p3.n pin is not skipped by the crossbar. 1: corresponding p3.n pin is skipped by the crossbar. note: p3.1?3.7 are only available on 48-pin devices. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xdf bits7?0: p4.[7:0] write - output appears on i/o pins. 0: logic low output. 1: logic high output (high impedance if corresponding p4mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p4mdin. directly reads port pin when configured as digital input. 0: p4.n pin is logic low. 1: p4.n pin is logic high. note: p4 is only available on 48-pin devices. r/w r/w r/w r/w r/w r/w r/w r/w reset value p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc7
rev. 1.3 157 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 15.21. p4mdin: port4 input mode sfr definition 15.22. p4mdout: port4 output mode bits7?0: analog input configuration bits for p4.7?p4.0 (respectively). port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p4.n pin is configured as an analog input. 1: corresponding p4.n pin is not configured as an analog input. note: p4 is only available on 48-pin devices. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xf5 bits7?0: output configuration bits for p4.7?p4.0 (res pectively); ignored if corresponding bit in regis- ter p4mdin is logic 0. 0: corresponding p4.n output is open-drain. 1: corresponding p4.n output is push-pull. note: p4 is only available on 48-pin devices. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xae
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 158 rev. 1.3 table 15.1. port i/o dc electri cal characteristics v dd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull v dd ? 0.7 v dd ? 0.1 v dd ? 0.8 v output low voltage i ol = 8.5 ma i ol = 10 a i ol = 25 ma 1.0 0.6 0.1 v input high voltage 2.0 v input low voltage 0.8 v input leakage current weak pull-up off weak pull-up on, v in = 0 v 25 1 50 a
rev. 1.3 159 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 16. universal serial bus controller (usb0) c8051f34x devices include a complete full/low sp eed usb function for usb peripheral implementa - tions*. the usb function controller (usb0) consists of a ser ial interface engine (sie), usb transceiver (including matching resistors and configurable pull-up resistors), 1k fifo block, and clock recovery mech - anism for crystal-less operation. no external com pon ents are required. the usb function controller and transceiver is universal serial bus specification 2.0 compliant. figure 16.1. usb0 block diagram important note: this document assumes a comprehensive understanding of the usb protocol. terms and abbreviations used in th is document are defined in the usb specifi- cation. we encourage you to review the latest version of the usb specification before pro- ceeding. *note: the c8051f34x cannot be used as a usb host device. transceiver serial interface engine (sie) usb fifos (1k ram) d+ d- vdd endpoint0 in/out endpoint1 in out endpoint2 in out endpoint3 in out data transfer control cip-51 core usb control, status, and interrupt registers
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 160 rev. 1.3 16.1. endpoint addressing a total of eight endpoint pipes are available. the control endpoint (endpoint0) always functions as a bi-directional in/out endpoint. the other endpoints are implemented as three pairs of in/out endpoint pipes: 16.2. usb transceiver the usb transceiver is configured via the usb0xcn register shown in sfr definition 16.1 . this configu - ration includes transceiver enable/disable, pull-up resistor e nable/disable, and device speed selection (full or low speed). when bit speed = ?1?, usb0 operates as a full speed usb function, and the on-chip pull-up resistor (if enabled) appears on the d+ pin. w hen bit speed = ?0?, usb0 operates as a low speed usb function, and the on-chip pull-up resistor (if ena bled) appears on the d- pin. bits4-0 of register usb0xcn can be used for transceiver testing as described in sfr definition 16.1 . the pull-up resistor is enabled only when vbus is present (see section ?8.2. vbus detection? on page 69 for details on vbus detection). important note: the usb clock should be active before the transceiver is enabled. table 16.1. endpoint addressing scheme endpoint associated pipes usb protocol address endpoint0 endpoint0 in 0x00 endpoint0 out 0x00 endpoint1 endpoint1 in 0x81 endpoint1 out 0x01 endpoint2 endpoint2 in 0x82 endpoint2 out 0x02 endpoint3 endpoint3 in 0x83 endpoint3 out 0x03
rev. 1.3 161 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 16.1. usb0xcn: usb0 transceiver control bit7: pren: internal pu ll-up resistor enable the location of the pull-up resistor (d + or d?) is determined by the speed bit. 0: internal pull-up resistor disabled (devic e effectively detached from the usb network). 1: internal pull-up resistor enabled when vbus is present (device attached to the usb net- work). bit6: phyen: physical layer enable this bit enables/disables the usb0 physical layer transceiver. 0: transceiver disabled (suspend). 1: transceiver enabled (normal). bit5: speed: usb0 speed select this bit selects the usb0 speed. 0: usb0 operates as a low speed device. if enabled, the internal pull-up resistor appears on the d? line. 1: usb0 operates as a full speed device. if en abled, the internal pull-up resistor appears on the d+ line. bits4?3: phytst1?0: physical layer test these bits can be used to test the usb0 transceiver. bit2: dfrec: differential receiver the state of this bit indicates the current differential value present on the d+ and d? lines when phyen = ?1?. 0: differential ?0? signaling on the bus. 1: differential ?1? signaling on the bus. bit1: dp: d+ signal status this bit indicates the current logic level of the d+ pin. 0: d+ signal currently at logic 0. 1: d+ signal currently at logic 1. bit0: dn: d- signal status this bit indicates the current logic level of the d? pin. 0: d? signal currently at logic 0. 1: d? signal currently at logic 1. r/w r/w r/w r/w r/w r r r reset value pren phyen speed phytst1 phytst0 dfrec dp dn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd7 phytst[1:0] mode d+ d? 00b mode 0: normal (non-test mode) x x 01b mode 1: differential ?1? forced 1 0 10b mode 2: differential ?0? forced 0 1 11b mode 3: single-ended ?0? forced 0 0
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 162 rev. 1.3 16.3. usb register access the usb0 controller registers listed in ta b l e 16.2 are accessed through two sfrs: usb0 address (usb0adr) and usb0 dat a (usb0dat). the usb0adr register se lects which usb register is targeted by reads/writes of the usb0dat register. see figure 16.2 . endpoint control/status registers ar e accessed by fir st writing the usb re gister index with the target end - point number. once the target endpoint number is writ te n to the index register, the control/status registers associated with the target endpoint may be a ccessed. see the ?indexed registers? section of ta b l e 16.2 for a list of endpoint control/status registers. important note: the usb clock must be active when accessing usb registers. figure 16.2. usb0 re gister access scheme usb controller fifo access index register endpoint0 control/ status registers endpoint1 control/ status registers endpoint2 control/ status registers endpoint3 control/ status registers common registers interrupt registers 8051 sfrs usb0adr usb0dat
rev. 1.3 163 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 16.2. usb0adr: usb0 indirect address bits7: busy: usb0 register read busy flag this bit is used during indirect usb0 register ac cesses. software should wr ite ?1? to this bit to initiate a read of the usb0 register targeted by the usbad dr bits (usb0adr.[5-0]). the target address and busy bit may be written in the same write to usb0 adr. after busy is set to ?1?, hardware will clear busy when th e targeted register data is ready in the usb0dat register. software should check busy for ?0? before writing to usb0dat. write: 0: no effect. 1: a usb0 indirect register read is initiate d at the address specified by the usbaddr bits. read: 0: usb0dat register data is valid. 1: usb0 is busy accessing an indirect register; usb0dat register data is invalid. bit6: autord: usb0 register auto-read flag this bit is used for block fifo reads. 0: busy must be written manually for each usb0 indirect register read. 1: the next indirect register read will automa tically be initiated when software reads usb0dat (usbaddr bits will not be changed). bits5?0: usbaddr: usb0 indi rect register address these bits hold a 6-bit address used to indirectly access the usb0 core registers. table 16.2 lists the usb0 core registers and their indire ct addresses. reads and writes to usb0dat will target the register in dicated by the usbaddr bits. r/w r/w r/w r/w r/w r/w r/w r/w reset value busy autord usbaddr 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x96
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 164 rev. 1.3 sfr definition 16.3. usb0dat: usb0 data this sfr is used to indirectly read and write usb0 registers. write procedure: 1. poll for busy (usb 0adr.7) => ?0?. 2. load the target usb0 register address into the usbaddr bits in register usb0adr. 3. write data to usb0dat. 4. repeat (step 2 may be skipped when writing to the same usb0 register). read procedure: 1. poll for busy (usb 0adr.7) => ?0?. 2. load the target usb0 register address into the usbaddr bits in register usb0adr. 3. write ?1? to the busy bit in register usb0adr (steps 2 and 3 can be performed in the same write). 4. poll for busy (usb 0adr.7) => ?0?. 5. read data from usb0dat. 6. repeat from step 2 (step 2 may be skipped when reading the same usb0 register; step 3 may be skipped when the autord bit (usb0adr.6) is logic 1). r/w r/w r/w r/w r/w r/w r/w r/w reset value usb0dat 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x97
rev. 1.3 165 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d usb register definition 16.4. index: usb0 endpoint index table 16.2. usb0 controller registers usb register name usb register address description page number interrupt registers in1int 0x02 endpoint0 and endpoints1-3 in interrupt flags 173 out1int 0x04 endpoints1-3 out interrupt flags 173 cmint 0x06 common usb interrupt flags 174 in1ie 0x07 endpoint0 and endpoints1-3 in interrupt enables 175 out1ie 0x09 endpoints1-3 out interrupt enables 175 cmie 0x0b common usb in terrupt enables 176 common registers faddr 0x00 function address 169 power 0x01 power management 171 framel 0x0c frame number low byte 172 frameh 0x0d frame number high byte 172 index 0x0e endpoint index selection 165 clkrec 0x0f clock recovery control 166 fifon 0x20?0x23 endpoints0-3 fifos 168 indexed registers e0csr 0x11 endpoint0 control / status 179 eincsrl endpoint in control / status low byte 182 eincsrh 0x12 endpoint in control / status high byte 183 eoutcsrl 0x14 endpoint out control / status low byte 185 eoutcsrh 0x15 endpoint out control / status high byte 186 e0cnt 0x16 number of received bytes in endpoint0 fifo 180 eoutcntl endpoint out packet count low byte 186 eoutcnth 0x17 endpoint out packet count high byte 186 bits7?4: unused. read = 0000b; write = don?t care. bits3?0: epsel: endpoint select these bits select which endpoint is target ed when indexed usb0 registers are accessed. r r r r r/w r/w r/w r/w reset value - - - - epsel 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0e index target endpoint 0x0 0 0x1 1 0x2 2 0x3 3 0x4?0xf reserved
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 166 rev. 1.3 16.4. usb clock configuration usb0 is capable of communication as a full or low speed usb function. communication speed is selected via the speed bit in sfr usb0xcn. when operati ng as a low speed func tion, the usb0 clock must be 6 mhz. when operating as a full speed fu nction, the usb0 clock must be 48 mhz. clock options a re described in section ?14. oscillators? on page 131 . the usb0 clock is selected via sfr clksel (see sfr definition 14.6 ). clock recovery circuitr y uses the incoming usb data stream to adjust the internal oscilla tor; this allows the internal oscillator (and 4x clock multiplier) to me et the requirements for usb clock tolerance. clock recovery should be used in the following configurations: when operating usb0 as a low speed function with clock recovery, software must write ?1? to the crlow bit to enable low speed clock recovery. clock recovery is typically no t necessary in low speed mode. single step mode can be used to help the clock recovery circuitry to lock when high noise levels are pres - ent on the usb network. this mode is not require d (or recommended) in typical usb environments. usb register definition 16.5. cl krec: clock recovery control communication speed usb clock 4 x clock multiplier input full speed 4x clock multip lier internal oscillator low speed internal oscillator / 2 n/a bit7: cre: clock recovery enable. this bit enables/disables the usb clock recovery feature. 0: clock recovery disabled. 1: clock recovery enabled. bit6: crssen: clock recovery single step. this bit forces the os cillator calibration into ?single-step? mode du ring clock recovery. 0: normal calibration mode. 1: single step mode. bit5: crlow: low speed clock recovery mode. this bit must be set to ?1? if clock recovery is used when operating as a low speed usb device. 0: full speed mode. 1: low speed mode. bits4?0: reserved. read = variable. must write = 01001b. note: the usb transceiver must be enabled before enabling clock recovery. r/w r/w r/w r/w r/w r/w r/w r/w reset value cre crssen crlow reserved 00001001 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0f
rev. 1.3 167 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 16.5. fifo management 1024 bytes of on-chip xram are used as fifo sp ace for usb0. this fifo space is split between endpoints0-3 as shown in figure 16.3 . fifo space allocated for endpoints1-3 is configurable as in, out, or both (split mode: half in, half out). figure 16.3. usb fifo allocation 16.5.1. fifo split mode the fifo space for endpoints1-3 can be split such that the upper half of the fifo space is used by the in endpoint, and the lower half is used by the out endpoint . for example: if the end point3 fifo is configured for split mode, the upper 256 bytes (0x0540 to 0x063f) are used by endpoint3 in and the lower 256 bytes (0x0440 to 0x053f) are used by endpoint3 out. if an endpoint fifo is not configured for split mode, that endpoint in/out pair?s fifos are combined to form a s ingle in or out fifo. in this case only one direction of the endpoint in/out pair may be used at a time. the endpoint direction (in/out) is determined by the dirsel bit in the corresponding endpoint?s eincsrh register (see sfr definition 16.20 ). endpoint0 (64 bytes) configurable as in, out, or both (split mode) free (64 bytes) 0x0400 0x043f 0x0440 0x063f 0x0640 0x073f 0x0740 0x07bf 0x07c0 0x07ff user xram (1024 bytes) 0x0000 0x03ff usb clock domain system clock domain endpoint1 (128 bytes) endpoint2 (256 bytes) endpoint3 (512 bytes)
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 168 rev. 1.3 16.5.2. fifo double buffering fifo slots for endpoints1-3 can be configured for double-buffered mode. in this mode, the maximum packet size is halved and the fifo may contain tw o packets at a time. this mode is available for endpoints1-3. when an endpoint is configured for split mode, double buffering may be enabled for the in endpoint and/or the out endpoint. when split mode is not enabled, double-buffering may be enabled for the entire endpoint fifo. see ta b l e 16.3 for a list of maximum packet sizes for each fifo configuration. 16.5.1. fifo access each endpoint fifo is accessed through a corresponding fifon register. a read of an endpoint fifon register unloads one byte from the fifo; a write of an endpoint fifon register loads one byte into the end - point fifo. when an endpoint fifo is configured for split mode, a read of the endpoint fifon register un loads one byte from the out endpoint fifo; a write of the endpoint fifon register loads one byte into the in endpoint fifo. usb register definition 16.6. fi fon: usb0 endpoint fifo access table 16.3. fifo configurations endpoint number split mode enabled? maximum in packet size (dou- ble buffer disabled / enabled) maximum out packet size (double buffer disabled / enabled) 0n / a 6 4 1 n 128 / 64 y 64 / 32 64 / 32 2 n 256 / 128 y 128 / 64 128 / 64 3 n 512 / 256 y 256 / 128 256 / 128 usb addresses 0x20?0x23 provide access to the 4 pairs of endpoint fifos: writing to the fifo address loads data into the in fifo for the corresponding endpoint. reading from the fifo address unloads data from the out fifo for the corresponding endpoint. r/w r/w r/w r/w r/w r/w r/w r/w reset value fifodata 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x20 - 0x23 in/out endpoint fifo usb address 00 x 2 0 10 x 2 1 20 x 2 2 30 x 2 3
rev. 1.3 169 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 16.6. function addressing the faddr register holds the current usb0 function address. software should write the host-assigned 7-bit function address to the faddr register when received as part of a set_address command. a new address written to faddr will not take effect (usb0 will not respond to the new address) until the end of the current transfer (typic ally following the status phase of the set_address command transfer). the update bit (faddr.7) is set to ?1? by hardware when software writes a new address to the faddr regis - ter. hardware clears the update bit when the new address takes effect as described above. usb register definition 16.7. faddr: usb0 function address 16.7. function configur ation and control the usb register power ( sfr definition 16.8 ) is used to configure and control usb0 at the device level (enable/disable, reset/suspend/resume handling, etc.). usb reset: the usbrst bit (power.3) is set to ?1? by hardware when reset signaling is detected on the bus. upon this detection, the following occur: 1. the usb0 address is reset (faddr = 0x00). 2. endpoint fifos are flushed. 3. control/status registers are reset to 0x 00 (e0csr, eincsrl, eincsrh, eoutcsrl, eoutcsrh). 4. usb register index is reset to 0x00. 5. all usb interrupts (excluding the suspend interrupt) are enabled and their corresponding flags clea red. 6. a usb reset interrupt is generated if enabled. writing a ?1? to the usbrst bit will generate an asynch ronous u sb0 reset. all u sb registers are reset to their default values following this asynchronous reset. suspend mode: with suspend detection enab led (susen = ?1?), usb0 w ill enter suspend mode when suspend signaling is detected on the bus. an inte rrupt will be generated if e nabled (susinte = ?1?). the suspend interrupt service routine (isr) should perfor m application-specific conf iguration tasks such as disabling appropriate peripherals and/or configuring clock sources for low power modes. see section bit7: update: function address update set to ?1? when software writes the faddr register. usb0 clears this bit to ?0? when the new address takes effect. 0: the last address written to faddr is in effect. 1: the last address written to faddr is not yet in effect. bits6?0: function address holds the 7-bit function address for usb0. this address should be written by software when the set_address standard device request is received on endpoint0. the new address takes effect when the device request completes. r r/w r/w r/w r/w r/w r/w r/w reset value update function address 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x00
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 170 rev. 1.3 ?14. oscillators? on page 131 for more details on internal oscillator configuration, in cluding the suspend mode feature of the internal oscillator . usb0 exits suspend mode when any of the following occu r: (1) resume signaling is detected or gener - ated, (2) reset signaling is detected, or (3) a device or usb r eset occurs. if suspended, the internal oscil - lator will exit suspe nd mode upon any of th e above liste d events. resume signaling: usb0 will exit suspend mode if resume signaling is det ected on the bus. a resume interrupt will be generat ed upon detection if enabled (resinte = ?1?). so ftware may force a remote wakeup by writing ?1? to the resume bit (power.2). when forcing a remote wakeup, software should write resume = ?0? to end resume signaling 10-15 ms after the remote wakeup is initiated (resu me = ?1?). iso update: when software writes ?1? to the isoup bit (power.7), th e iso update function is enabled. with iso update enabled, new packets written to an iso in endpoint will not be transmitted until a new start-of-frame (sof) is re ceived. if the iso in endpoint receives an in token before a sof, usb0 will transmit a zero-length packet. when isoup = ?1?, iso update is enabled for all iso endpoints. usb enable: usb0 is disabled following a power-on-reset (por). usb0 is enabled by clearing the usbinh bit (power.4). once written to ?0?, the usbinh can only be set to ?1? by one of the following: (1) a power-on-reset (por), or (2) an asynchronous usb0 reset generated by writing ?1? to the usbrst bit (power.3). software should perform all usb0 configuration b efore enabling usb0. the configuration sequence should be performed as follows: step 1. select and enable the usb clock source. s tep 2. reset usb0 by writing usbrst= ?1?. step 3. configure and enable the usb transceiver. step 4. perform any usb0 function configuration (interrupts, suspend detect). step 5. enable usb0 by writing usbinh = ?0?.
rev. 1.3 171 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d usb register definition 16. 8. power: usb0 power bit7: isoud: iso update this bit affects all in isochronous endpoints. 0: when software writes inprdy = ?1?, usb0 w ill send the packet when the next in token is received. 1: when software writes inprdy = ?1?, usb0 will wait for a sof token before sending the packet. if an in token is received before a so f token, usb0 will send a zero-length data packet. bits6?5: unused. read = 00b. write = don?t care. bit4: usbinh: usb0 inhibit this bit is set to ?1? following a power-on reset (por) or an asynchronous usb0 reset (see bit3: reset). software should cl ear this bit after all usb0 an d transceiver initialization is complete. software canno t set this bit to ?1?. 0: usb0 enabled. 1: usb0 inhibited. all usb traffic is ignored. bit3: usbrst: reset detect writing ?1? to this bit forces an asynchronous usb0 reset. reading this bit provides bus reset status information. read: 0: reset signaling is not present on the bus. 1: reset signaling detected on the bus. bit2: resume: force resume software can force resume signaling on the bus to wake usb0 from suspend mode. writing a ?1? to this bit while in suspend mode (susmd = ?1?) forces usb0 to generate resume sig- naling on the bus (a remote wakeup event). software should writ e resume = ?0? after 10 ms to15 ms to end the resume signaling. an interrupt is generated, and hardware clears susmd, when software writes resume = ?0?. bit1: susmd: suspend mode set to ?1? by hardware when usb0 enters su spend mode. cleared by hardware when soft- ware writes resume = ?0? (fo llowing a remote wakeup) or reads the cmint register after detection of resume signaling on the bus. 0: usb0 not in suspend mode. 1: usb0 in suspend mode. bit0: susen: suspend detection enable 0: suspend detection disabled. usb0 w ill ignore suspend si gnaling on the bus. 1: suspend detectio n enabled. usb0 will ente r suspend mode if it de tects suspend signaling on the bus. r/w r/w r/w r/w r/w r/w r r/w reset value isoud - - usbinh usbrst resume susmd susen 00010000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x01
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 172 rev. 1.3 usb register definition 16.9. framel: usb0 frame number low usb register definiti on 16.10. frameh: us b0 frame number high 16.8. interrupts the read-only usb0 interrupt flags are located in the usb registers shown in usb register definition 16.11 through usb register definition 16.13 . the associated interrupt enable bits are located in the usb registers shown in usb register definition 16.14 through usb register definition 16.16 . a usb0 interrupt is generated when any of the usb interrupt fl ags is set to ?1?. the usb0 in terrupt is enabled via the eie1 sfr (see section ?9.3. interrupt handler? on page 88 ). important note: reading a usb interrupt flag regist er resets all flags in that register to ?0?. bits7-0: frame number low this register contains bits7-0 of the last received frame number. rrrrrrrrr e s e t v a l u e frame number low 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0c bits7-3: unused. read = 0. write = don?t care. bits2-0: frame number high byte this register contains bits10-8 of the last received frame number. rrrrrrrrr e s e t v a l u e - - - - - frame number high 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0d
rev. 1.3 173 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d usb register definition 16.11. in1i nt: usb0 in endpoint interrupt usb register definition 16.12. out1int: usb0 out endpoint interrupt bits7?4: unused. read = 0000b. write = don?t care. bit3: in3: in endpoint 3 interrupt-pending flag this bit is cleared when softwa re reads the in1int register. 0: in endpoint 3 interrupt inactive. 1: in endpoint 3 interrupt active. bit2: in2: in endpoint 2 interrupt-pending flag this bit is cleared when softwa re reads the in1int register. 0: in endpoint 2 interrupt inactive. 1: in endpoint 2 interrupt active. bit1: in1: in endpoint 1 interrupt-pending flag this bit is cleared when softwa re reads the in1int register. 0: in endpoint 1 interrupt inactive. 1: in endpoint 1 interrupt active. bit0: ep0: endpoint 0 interrupt-pending flag this bit is cleared when softwa re reads the in1int register. 0: endpoint 0 interrupt inactive. 1: endpoint 0 interrupt active. rrrrrrrrr e s e t v a l u e - - - - in3 in2 in1 ep0 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x02 bits7?4: unused. read = 0000b. write = don?t care. bit3: out3: out endpoint 3 interrupt-pending flag this bit is cleared when software reads the out1int register. 0: out endpoint 3 interrupt inactive. 1: out endpoint 3 interrupt active. bit2: out2: out endpoint 2 interrupt-pending flag this bit is cleared when software reads the out1int register. 0: out endpoint 2 interrupt inactive. 1: out endpoint 2 interrupt active. bit1: out1: out endpoint 1 interrupt-pending flag this bit is cleared when software reads the out1int register. 0: out endpoint 1 interrupt inactive. 1: out endpoint 1 interrupt active. bit0: unused. read = 0; write = don?t care. rrrrrrrrr e s e t v a l u e ----out3out2out1-00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x04
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 174 rev. 1.3 usb register definition 16.13. cmint: usb0 common interrupt bits7?4: unused. read = 0000b; write = don?t care. bit3: sof: start of frame interrupt set by hardware when a sof token is received. this interrupt event is synthesized by hard- ware: an interrupt will be generated when hardware expects to receiv e a sof event, even if the actual sof signal is missed or corrupted. this bit is cleared when software reads the cmint register. 0: sof interrupt inactive. 1: sof interrupt active. bit2: rstint: reset in terrupt-pending flag set by hardware when reset signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: reset interrupt inactive. 1: reset inte rrupt active. bit1: rsuint: resume interrupt-pending flag set by hardware when resume signaling is detected on the bus while usb0 is in suspend mode. this bit is cleared when software reads the cmint register. 0: resume interrupt inactive. 1: resume interrupt active. bit0: susint: suspend interrupt-pending flag when suspend detection is enabled (bit susen in register power), this bit is set by hard- ware when suspend signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: suspend interrupt inactive. 1: suspend interrupt active. rrrrrrrrr e s e t v a l u e - - - - sof rstint rsuint susint 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x06
rev. 1.3 175 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d usb register definition 16. 14. in1ie: usb0 in endpoint interrupt enable usb register definition 16.15. out1ie: usb0 out endpoint interrupt enable bits7?4: unused. read = 0000b. write = don?t care. bit3: in3e: in endpoint 3 interrupt enable 0: in endpoint 3 interrupt disabled. 1: in endpoint 3 interrupt enabled. bit2: in2e: in endpoint 2 interrupt enable 0: in endpoint 2 interrupt disabled. 1: in endpoint 2 interrupt enabled. bit1: in1e: in endpoint 1 interrupt enable 0: in endpoint 1 interrupt disabled. 1: in endpoint 1 interrupt enabled. bit0: ep0e: endpoint 0 interrupt enable 0: endpoint 0 interrupt disabled. 1: endpoint 0 interrupt enabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - in3e in2e in1e ep0e 00001111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x07 bits7?4: unused. read = 0000b. write = don?t care. bit3: out3e: out endpoint 3 interrupt enable 0: out endpoint 3 interrupt disabled. 1: out endpoint 3 interrupt enabled. bit2: out2e: out endpoint 2 interrupt enable 0: out endpoint 2 interrupt disabled. 1: out endpoint 2 interrupt enabled. bit1: out1e: out endpoint 1 interrupt enable 0: out endpoint 1 interrupt disabled. 1: out endpoint 1 interrupt enabled. bit0: unused. read = 0; write = don?t? care. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - out3e out2e out1e - 00001110 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x09
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 176 rev. 1.3 usb register definition 16.16. cm ie: usb0 common interrupt enable 16.9. the serial interface engine the serial interface engine (sie) performs all low level usb protocol tasks, interrupting the processor when data has successfully been trans mitted or received. when receivin g data, the sie w ill interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automat - ically generated by the sie. when tr ansmitting data, the sie will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received. the sie will not interrupt the processor when corr upted/erroneous packets are received. 16.10. endpoint0 endpoint0 is managed through the usb register e0csr ( usb register definition 16.17 ). the index reg - ister must be loaded with 0x00 to access the e0csr register. an endpoint0 interrupt is generated when: 1. a data packet (out or setup) has been received and loaded into the endpoint0 fifo. the opr dy bit (e0csr.0) is set to ?1? by hardware. 2. an in data packet has successfully been unloaded from the endpoint0 fifo and transmitted to the host ; inprdy is re set to ?0? by hardware. 3. an in transaction is completed (this interrupt generated during the status stage of the transac - tion). 4. hardware sets the ststl bit (e0csr.2) after a control transaction ended due to a protocol viola tion. 5. hardware sets the suend bit (e0csr.4) beca use a control transfer ended before firmware sets the dataend bit (e0csr.3). bits7?4: unused. read = 0000b; write = don?t care. bit3: sofe: start of frame interrupt enable 0: sof interrupt disabled. 1: sof interrupt enabled. bit2: rstinte: reset interrupt enable 0: reset interrupt disabled. 1: reset interrupt enabled. bit1: rsuinte: resume interrupt enable 0: resume interrupt disabled. 1: resume interrupt enabled. bit0: susinte: suspend interrupt enable 0: suspend interrupt disabled. 1: suspend interrupt enabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - sofe rstinte rsuinte susinte 00000110 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0b
rev. 1.3 177 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d the e0cnt register ( usb register definition 16.18 ) holds the number of received data bytes in the endpoint0 fifo. hardware will automatically detect protocol errors and send a stal l condition in resp onse. firmware may force a stall condition to abort the current transfer. when a stall condition is generated, the ststl bit will be set to ?1? and an interrupt generated. the followi ng conditions will cause ha rdware to generate a stall condition: 1. the host sends an out token during a out data phase after the dataend bit has been set to ?1?. 2. the host sends an in token during an in data phase after the dataend bit has been set to ?1?. 3. the host sends a packet that exceeds the maximum packet size for endpoint0. 4. the host sends a non-zero length data1 packet during the status phase of an in transaction. 5. firmware sets the sdstl bit (e0csr.5) to ?1?. 16.10.1.endpoint0 setup transactions all control transfers must begin with a setup packet. setup packets are similar to out packets, contain - ing an 8-byte data field sent by the host. any setup p acket containing a command field of anything other than 8 bytes will be automatically rejected by usb0. an endpoint0 inte rrupt is generate d when the data from a setup packet is loaded into the endpoint0 fifo. software should unload the command from the endpoint0 fifo, decode the command, perform any necess ary tasks, and set the soprdy bit to indicate that it has serviced the out packet. 16.10.2.endpoint0 in transactions when a setup request is received that requires usb0 to transmit data to the host, one or more in requests will be sent by the host. fo r the first in transaction, firmware should load an in packet into the endpoint0 fifo, and set the inprdy bi t (e0csr.1). an interr upt will be generated w hen an in packet is transmitted successfully. note that no interrupt will be generated if an in requ est is receiv ed before firm - ware has loaded a packet into the endpoint0 fifo. if the requested data exceeds the maximum packet size for endpoint0 (as reported to the host), the data should be split into multiple packets; each packet should be of the maximum packet size excluding the last (residual) packet. if the requested data is an inte - ger multiple of the maximum packet size for endpoint 0, the last data packet should be a zero-length packet signaling the end of the transfer. firmware should set the dataend bit to ?1? after loading into the endpoint0 fifo the last data packet for a transfer. upon reception of the first in token for a particular contr ol transfer, endpoint0 is said to be in transmit mode. in this mode, only in tokens should be sent by the host to en dpoint0. the suend bit (e0csr.4) is set to ?1? if a setup or out token is rece ived while endpoint0 is in transmit mode. endpoint0 will remain in transmit mode until any of th e following occur: 1. usb0 receives an endpoint0 setup or out token. 2. firmware sends a packet less than the maximum endpoint0 packet size. 3. firmware sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to ?1? when performing (2) and (3) above. the sie will transmit a nak in response to an in token if there is no packet ready in the in fifo (inprdy = ?0?).
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 178 rev. 1.3 16.10.3.endpoint0 out transactions when a setup request is received that requires the host to transmit data to usb0, one or more out requests will be sent by the host. w hen an out packet is su ccessfully received by usb0, hardware will set the oprdy bit (e0csr.0) to ?1? and generate an endpoint0 interrupt. following this interrupt, firmware should unload the out packet from the endpoint0 fifo and set the soprdy bit (e0csr.6) to ?1?. if the amount of data required for the transfer exceeds the maximum packet size for endpoint0, the data will be split into multiple p ackets. if the requested data is an integer multiple of the maximum packet size for endpoint0 (as reported to the host), the host will send a zero-l ength data packet signaling the end of the transfer. upon reception of the first out token for a particular co ntrol transfer, endpoint0 is said to be in receive mode. in this mode, only out tokens should be sent by the host to endpoint0. the suend bit (e0csr.4) is set to ?1? if a setup or in token is received while endpoint0 is in receive mode. endpoint0 will remain in recei ve mode until: 1. the sie receives a setup or in token. 2. the host sends a packet less than the maximum endpoint0 packet size. 3. the host sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to ?1? when the expected amount of data has been received. the sie will transmit a st all condition if the host sends an out packet after the dataend bit has been set by firmware. an interr upt will be generated with the ststl bit (e0c sr.2) set to ?1? after the stall is transmitted.
rev. 1.3 179 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d usb register definiti on 16.17. e0csr: usb0 endpoint0 control bit7: ssuend: serviced setup end write: software should set this bit to ?1? afte r servicing a setup end (bit suend) event. hardware clears the suend bit when software writes ?1? to ssuend. read: this bit always reads ?0?. bit6: soprdy: serviced oprdy write: software should write ?1? to this bit after servicing a received endpoint0 packet. the oprdy bit will be cleared by a write of ?1? to soprdy. read: this bit always reads ?0?. bit5: sdstl: send stall software can write ?1? to this bi t to terminate the current transfer (due to an error condition, unexpected transfer request, etc.). hardware will clear this bit to ?0? when the stall hand- shake is transmitted. bit4: suend: setup end hardware sets this read-only bit to ?1? when a control transaction ends before software has written ?1? to the dataend bit. hardware clears this bit when software writes ?1? to ssu- end. bit3: dataend: data end software should write ?1? to this bit: 1. when writing ?1? to inprdy for the last outgoing data packet. 2. when writing ?1? to inprdy for a zero-length data packet. 3. when writing ?1? to soprdy after servicing the last incoming data packet. this bit is automatically cleared by hardware. bit2: ststl: sent stall hardware sets this bit to ?1? after transmitting a stall handshake signal. this flag must be cleared by software. bit1: inprdy: in packet ready software should write ?1? to this bit after l oading a data packet into the endpoint0 fifo for transmit. hardware clear s this bit and generates an interrupt under either of the following conditions: 1. the packet is transmitted. 2. the packet is overwritten by an incoming setup packet. 3. the packet is overwritten by an incoming out packet. bit0: oprdy: out packet ready hardware sets this read-only bit and generat es an interrupt when a data packet has been received. this bit is cleared only when software writes ?1? to the soprdy bit. r/w r/w r/w r r/w r/w r/w r reset value ssuend soprdy sdstl suend dataend ststl inprdy oprdy 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x11
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 180 rev. 1.3 usb register definiti on 16.18. e0cnt: usb0 endpoint 0 data count 16.11. configuring endpoints1-3 endpoints1-3 are configured and cont rolled through their own sets of the following control/status registers: in registers eincsrl and eincsrh, and out regi sters eoutcsrl and eoutcsrh. only one set of endpoint control/status registers is mapped into the usb register address space at a time, defined by the contents of the index register ( usb register definition 16.4 ). endpoints1-3 can be configured as in, out, or both in/out (split mode) as described in section 16.5.1 . the endpoint mode (split/normal) is selected via the split bit in register eincsrh. when split = ?1?, the corresponding endpoint fifo is sp lit, and both in and out pipes are available. when split = ?0?, the corresponding endpoint functions as either in or out; th e endpoint direction is selected by the dirsel bit in register eincsrh. 16.12. controlling endpoints1-3 in endpoints1-3 in are managed via usb registers einc srl and eincsrh. all in endpoints can be used for interrupt, bulk, or isoc hronous transfers. isochronous (iso) mode is enabled by writing ?1? to the iso bit in register eincsrh. bulk and interrupt transfers are handled identically by hardware. an endpoint1-3 in interrupt is generate d by any of the following conditions: 1. an in packet is successfully transferred to the host. 2. software writes ?1? to the flush bit (eincs rl .3) when the target fifo is not empty. 3. hardware generates a stall condition. 16.12.1.endpoints1-3 in interrupt or bulk mode when the iso bit (eincsrh.6) = ?0? the target endpoint operates in bulk or interrupt mode. once an end - point has been configured to operate in bulk/inter rupt in mode (typically following an endpoint0 set_interface command), firmware should load an in packet into the endpoint in fifo and set the inprdy bit (eincsrl.0). upon reception of an in token, hardware will tran smit the data, clear the inprdy bit, and generate an interrupt. bit7: unused. read = 0; write = don?t care. bits6?0: e0cnt: endpoint 0 data count this 7-bit number indicates the number of received data bytes in the endpoint 0 fifo. this number is only valid wh ile bit oprdy is a ?1?. rrrrrrrrr e s e t v a l u e - e0cnt 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x16
rev. 1.3 181 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d writing ?1? to inprdy without writin g any data to the endpoint fifo w ill cause a zero-length packet to be transmitted upon reception of the next in token. a bulk or interrupt pipe can be shut down (or halted) by writing ?1? to the sdstl bit (eincsrl.4). while sdstl = ?1?, hardware will respond to all in requests with a stall condition. ea ch time hardware gener - ates a stall condition, an interr upt will be generated an d the ststl bit (eincsrl.5) set to ?1?. the ststl bit must be rese t to ?0? by firmware. hardware will automatically re set inprd y to ?0? when a packet slot is open in the endpoint fifo. note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the in fifo at a time. in this case, hardware will reset inprdy to ?0? immediately after firmware loads the first packet into the fifo and sets inprdy to ?1?. an interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. when firmware writes ?1? to the fcdt bit (eincsrh.3) , the dat a toggle for each in packet will be toggled continuously, regardless of the handshake received from the host. this feature is typically used by inter - rupt endpoints functioning as rate feedback communica tio n for isochronous endpoints. when fcdt = ?0?, the data toggle bit will only be togg led when an ack is sent from the host in response to an in packet. 16.12.2.endpoints1-3 in isochronous mode when the iso bit (eincsrh.6) is set to ?1?, the target endpoint operates in isochronous (iso) mode. once an endpoint has been config ured for iso in mode, the host will se nd one in token (d ata request) per frame; the location of data within each frame may vary. because of this, it is recommended that double buffering be enabled for iso in endpoints. hardware will automatically reset in prdy (eincsr l.0) to ?0? when a pack et slot is open in the endpoint fifo. note that if double buffering is enabled for the ta rget endpoint, it is possible for firmware to load two packets into the in fifo at a time . in this case, hardware will reset in prdy to ?0? immediately after firm - ware loads the first packet in to the fifo and set s inprdy to ?1?. an interrupt will not be generated in this case; an interrupt will on ly be generated when a data packet is transmitted. if there is not a data packet ready in the endpoint fifo when usb0 receives an in token from the host, usb0 will transmit a zero-length data packet and set the undrun bit (eincsrl.2) to ?1?. the iso update feature (see section 16.7 ) can be useful in starting a double buffered iso in endpoint. if the host has already set up the iso in pipe (has b egu n transmitting in tokens) when firmware writes the first data packet to the endpoint fifo, the next in to ken may arrive and the first data packet sent before firmware has written the second (double buffered ) data packet to the fifo. the iso update feature ensures that any data packet written to the endpoint fi fo will not be transmitted during the current frame; the packet will only be sent after a sof signal has been received.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 182 rev. 1.3 usb register definition 16.19. eincsrl: usb0 in endpoint control low byte bit7: unused. read = 0; write = don?t care. bit6: clrdt: clear data toggle. write: software should write ?1? to this bit to reset the in endpoint data toggle to ?0?. read: this bit always reads ?0?. bit5: ststl: sent stall hardware sets this bit to ?1? when a stall handshake signal is transmitted. the fifo is flushed, and the inprdy bit cleared. this flag must be cleared by software. bit4: sdstl: send stall. software should write ?1? to this bit to generate a stall handshake in response to an in token. software should write ?0? to this bit to terminate the stall signal. this bit has no effect in iso mode. bit3: flush: fifo flush. writing a ?1? to this bit flushes the next packet to be transmitted from the in endpoint fifo. the fifo pointer is reset and the inprdy bit is cleared. if the fifo contains multiple pack- ets, software must write ?1? to flush for each packet. hardware resets the flush bit to ?0? when the fifo flush is complete. bit2: undrun: data underrun. the function of this bit depends on the in endpoint mode: isochronous: set when a zero-length packet is se nt after an in token is received while bit inprdy = ?0?. interrupt/bulk: this bit is not used in these modes and will always read a '0'. this bit must be cleared by software. bit1: fifone: fifo not empty. 0: the in endpoint fifo is empty. 1. the in endpoint fifo contains one or more packets. bit0: inprdy: in packet ready. software should write ?1? to this bit after l oading a data packet into the in endpoint fifo. hardware clears inprdy due to any of the following: 1. a data packet is transmitted. 2. double buffering is enabled (dbien = ?1 ?) and there is an open fifo packet slot. 3. if the endpoint is in isoc hronous mode (iso = ?1 ?) and isoud = ?1?, inprdy will read ?0? until the next sof is received. an interrupt (if enabled) will be generated when hardware clears inprdy as a result of a packet being transmitted. r w r/w r/w r/w r/w r/w r/w reset value - clrdt ststl sdstl flush undrun fifone inprdy 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x11
rev. 1.3 183 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d usb register definition 16. 20. eincsrh: usb0 in en dpoint control high byte 16.13. controlling endpoints1-3 out endpoints1-3 out are managed via usb registers eoutcsrl and eoutcsrh. all out endpoints can be used for interr upt, bulk, or isochronous transfers. isochronou s (iso) mode is enabled by writing ?1? to the iso bit in register eoutcsrh. bulk and interr upt transfers are handled identically by hardware. an endpoint1-3 out interrupt may be generated by the following: 1. hardware sets the oprd y bit (ein csrl.0) to ?1?. 2. hardware generates a stall condition. 16.13.1.endpoints1-3 out interrupt or bulk mode when the iso bit (eoutcsrh.6) = ?0? the target endpoi nt operates in bulk or interrupt mode. once an endpoint has been configured to operate in bulk/interrupt out mode (typically following an endpoint0 set_interface command), hardware will set the op rdy bit (eoutcsrl.0) to ?1? and generate an interrupt upon reception of an out token and data packet. the number of bytes in the current out data packet (the packet ready to be unloaded from the fifo) is given in the eoutcnth and eoutcntl reg - isters. in response to this interrup t, fir mware should unload the data packet from the out fifo and reset the oprdy bit to ?0?. bit7: dbien: in endpoint double-buffer enable. 0: double-buffering disabled for the selected in endpoint. 1: double-buffering enabled for the selected in endpoint. bit6: iso: isochronous transfer enable. this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. bit5: dirsel: endpoint direction select. this bit is valid only when the select ed fifo is not split (split = ?0?). 0: endpoint direction selected as out. 1: endpoint direction selected as in. bit4: unused. read = ?0?. write = don?t care. bit3: fcdt: force data toggle. 0: endpoint data toggle switches only when an ack is received following a data packet transmission. 1: endpoint data toggle forced to switch after ev ery data packet is transmitted, regardless of ack reception. bit2: split: fifo split enable. when split = ?1?, the selected endpoint fifo is split. the upper half of the selected fifo is used by the in endpoint; the lower half of th e selected fifo is used by the out endpoint. bits1?0: unused. read = 00b; write = don?t care. r/w r/w r/w r r/w r/w r r reset value dbien iso dirsel - fcdt split - - 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x12
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 184 rev. 1.3 a bulk or interrupt pipe can be shut down (or halted ) by writing ?1? to the sdstl bit (eoutcsrl.5). while sdstl = ?1?, hardware will respond to all out request s with a stall condi tion. each time hardware gen - erates a stall condition, an interr upt will be generated an d the ststl bit (eou tcsrl.6) set to ?1?. the ststl bit must be rese t to ?0? by firmware. hardware will automatically set op rdy when a packet is ready in th e out fifo. note th at if double buff - ering is enabled for the target endpoint, it is possible fo r two packets to be ready in the out fifo at a time. in this case, hardware will set oprdy to ?1? immediately after firmware unloads the first pa cket and resets oprdy to ?0?. a second interrupt will be generated in this case. 16.13.2.endpoints1-3 out isochronous mode when the iso bit (eoutcsrh.6) is set to ?1?, the target endpoint operates in isochronous (iso) mode. once an endpoint has been configured for iso out mode, the host will send exactly one data per usb frame; the location of the data packet within each frame may vary, however. because of this, it is recom - mended that double buffering be enabled for iso out endpoints. each time a data packet is received, hardware will l oad the received data packet into the endpoint fifo, set the oprdy bit (eoutcsrl.0) to ?1?, and generate an interrupt (if enabled). firmware would typically use this interrupt to unload the data packet from the endpoint fifo and reset the oprdy bit to ?0?. if a data packet is received when there is no room in the end point fifo, an inte rrupt will be generated and the ovrun bit (eoutcsrl.2) set to ?1?. if usb0 re ceives an iso data packet with a crc error, the data packet will be loaded into the endpoi nt fifo, oprdy will be set to ?1?, an interrupt (if enab led) will be gen - erated, and the dataerr bit (eoutcsrl.3) will be se t to ?1?. software should check the dataerr bit each time a data packet is unloaded from an iso out endpoint fifo.
rev. 1.3 185 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d usb register definition 16.21. eoutcsrl: usb0 out endpoint control low byte bit7: clrdt: clear data toggle write: software should write ?1? to this bit to reset the out endpoint data toggle to ?0?. read: this bit always reads ?0?. bit6: ststl: sent stall hardware sets this bit to ?1? when a stall handshake signal is transmitted. this flag must be cleared by software. bit5: sdstl: send stall software should write ?1? to this bit to generate a stall handshake. software should write ?0? to this bit to terminat e the stall signal. this bit has no effect in iso mode. bit4: flush: fifo flush writing a ?1? to this bit flushes the next packet to be read from the out endpoint fifo. the fifo pointer is reset and the oprdy bit is cleared. if the fifo contains multiple packets, software must write ?1? to fl ush for each packet. hardware resets the flush bit to ?0? when the fifo flush is complete. note: if data for the current packet has already been read from the fifo, the flush bit should not be used to flush the packet. instead, the entire data packet should be read from the fifo manually. bit3: daterr: data error in iso mode, this bit is set by hardware if a received packet has a crc or bit-stuffing error. it is cleared when software clears oprdy. this bit is only valid in iso mode. bit2: ovrun: data overrun this bit is set by hardware when an incoming data packet cannot be loaded into the out endpoint fifo. this bit is only valid in iso mode, and must be cleared by software. 0: no data overrun. 1: a data packet was lost because of a full fifo since this flag was last cleared. bit1: fifoful: out fifo full this bit indicates the contents of the out fifo . if double buffering is enabled for the end- point (dbien = ?1?), the fifo is full when the fi fo contains two packets. if dbien = ?0?, the fifo is full when the fifo contains one packet. 0: out endpoint fifo is not full. 1: out endpoint fifo is full. bit0: oprdy: out packet ready hardware sets this bit to ?1? and generates an interrupt when a data packet is available. soft- ware should clear this bit after each data packet is unloaded from the out endpoint fifo. w r/w r/w r/w r r/w r r/w reset value clrdt ststl sdstl flush daterr ovrun fifoful oprdy 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x14
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 186 rev. 1.3 usb register definition 16.22. eoutcsrh: usb0 out endpoint control high byte usb register definition 16.23. eoutcntl: usb0 out endpoint count low usb register definition 16.24. eoutcnth: usb0 out endpoint count high bit7: dboen: double-buffer enable 0: double-buffering disabled for the selected out endpoint. 1: double-buffering enabled for the selected out endpoint. bit6: iso: isochronous transfer enable this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. bits5?0: unused. read = 000000b; write = don?t care. r/w r/w r/w r/w r r r r reset value dboen iso - - - - - - 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x15 bits7?0: eocl: out endpoint count low byte eocl holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current out endpoint fifo. this num ber is only valid while oprdy = ?1?. rrrrrrrrr e s e t v a l u e eocl 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x16 bits7?2: unused. read = 00000. write = don?t care. bits1?0: eoch: out endpoint count high byte eoch holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current out endpoint fifo. this num ber is only valid while oprdy = ?1?. rrrrrrrrr e s e t v a l u e - - - - - - e0ch 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x17
rev. 1.3 187 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d table 16.4. usb transceiver electri cal characteristics v dd = 3.0 to 3.6 v, ?40 to +85 c unless otherwise specified parameters symbol conditions min typ max units transmitter output high voltage v oh 2.8 v output low voltage v ol 0.8 v output crossover point v crs 1.3 2.0 v output impedance z drv driving high driving low 38 38 ? pull-up resistance r pu full speed (d+ pull-up) low speed (d? pull-up) 1.425 1.5 1.575 k ? output rise time t r low speed full speed 75 4 300 20 ns output fall time t f low speed full speed 75 4 300 20 ns receiver differential input sensitivity v di | (d+) ? (d?) | 0.2 v differential input common mode range v cm 0.8 2.5 v input leakage current i l pullups disabled <1.0 a note: refer to the usb specification for timing diagrams and symbol definitions.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 188 rev. 1.3 17. smbus the smbus i/o interface is a two-wire, bi-directional se rial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i2c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonom ously controlling the serial transfer of the data. data can be transferre d at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or sla ve, and may function on a bus with multiple mas - ters. the smbus provides control of sda (serial data), scl ( serial clock) generation and synchronization, arbitration logic, and start/stop control and genera tion. three sfrs are associated with the smbus: smb0cf configures the sm bus; smb0cn controls the status of the smbus; and smb0dat is the data register, used for both transmitting and receiving smbus data and slave addresses. figure 17.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control arbitration scl synchronization irq generation scl generation (master mode) sda control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n
rev. 1.3 189 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 17.1. supporting documents it is assumed the reader is familiar with or has access to th e following suppo rting documents: 1. the i2c-bus and how to use it (including specifications), philip s semiconductor. 2. the i2c-bus specification -- ve rsion 2.0, philip s semiconductor. 3. system management bus specification -- v ersion 1.1, sbs implementers forum. 17.2. smbus configuration figure 17.2 shows a typical smbus configuration. the smbu s specification allow s any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-direc - tional scl (serial clock) and sda (serial data) lines mu st b e connected to a positive power supply voltage through a pull-up resistor or similar circuit. every device connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 17.2. typical smbus configuration 17.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbi tration. note that it is not necessary to specify one device as the master in a system ; any device who transmits a star t and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7-1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. each byte that is received (by a master or slave) must be acknowle dged (ack) with a low sda during a high scl (see figure 17.3 ). if the receiving devi ce does not ack, the transmitting device will read a nack (not acknowl - edge), which is a high sda during a high scl. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 190 rev. 1.3 the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and direction bit. if the trans - action is a write operation from the ma ster to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 17.3 illustrates a typical smbus transaction. figure 17.3. smbus transaction 17.3.1. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?17.3.4. scl high (smbus free) timeout? on page 191 ). in the event that two or more devices attemp t to begin a transfer at the same time, an arbi - tration scheme is employed to force one master to gi ve up the bus. the master devices continue transmit - ting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attempti ng the high will detect a low sda an d lose the arbitration. the win - ning master continues its transmission without interruption; the losing master becomes a slave and r eceives the rest of the transfer if addressed. this arbitration scheme is non-destructive: one device always wins, and no data is lost. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop
rev. 1.3 191 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 17.3.2. clock low extension smbus provides a clock synchronizati on mechanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extensio n is used during a transf er in order to allow slower slave devices to communicate with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 17.3.3. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi - cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to r eload when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to ov erflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable a nd re-enable) the smbus in the event of an scl low timeout. 17.3.4. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is designated as free. w hen the smbfte bit in smb0cf is set, the bus will be c onsidered free if scl and sda remain high for more than 10 smbus clock source periods. if the smbus is waiting to generate a master st art, the start will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave-only implementation. 17.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con - trol for serial transfers; higher level protocol is dete rm ined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as define d by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information smbus interrupts are generated for each data byte or slave ad dress that is transf erred. when transmitting, this interrupt is generated after the ack cycle so th at software may read the received ack value; when receiving data, this interrupt is generated before the ack cycle so that software may define the outgoing ack value. see section ?17.5. smbus transfer modes? on page 198 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus inte rrupt. the smb0cn register is described in section ?17.4.2. smb0cn control register? on page 195 ; table 17.4 provides a quick smb0cn decoding refer - ence.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 192 rev. 1.3 smbus configuration options include: ? timeout detection (scl low timeout and/or bus free timeout) ? sda setup and hold time extensions ? slave event enable/disable ? clock source selection these options are selected in the smb0cf register, as described in section ?17.4.1. smbus configura - tion register? on page 192 . 17.4.1. smbus configuration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options. when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus interface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave in terrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). the smbcs1-0 bits select the smbus clock source, which is used on ly when operating as a master or when the free timeout detection is enabled. when operating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 17.1 . note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uar t baud rates simultaneously. timer configuration is covered in section ?21. timers? on page 235 . equation 17.1. minimum scl high and low t imes the selected clock source should be configured to establish the minimum scl high and low times as per equation 17.1 . when the interface is operating as a master ( and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 17.2 . equation 17.2. typical smbus bit rate table 17.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == bitrate f clocksourceoverflow 3 --------------- ------------------------------ - =
rev. 1.3 193 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 17.4 shows the typical scl generation described by equation 17.2 . notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will never ex ceed the limits defined by equation equation 17.1 . figure 17.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. ta b l e 17.2 shows the min - imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low time outs (see section ?17.3.3. scl low timeout? on page 191 ). the smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count when scl is low. the timer 3 interrupt service rou - tine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detecti on can be enabled by setting the smbfte bi t. when this bit is set, the bus will b e considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 17.4 ). when a free timeout is dete cted, the interface w ill respond as if a stop was detected (an interrupt will be generat ed, and st o will be set). table 17.2. minimum sda setup and hold times exthold minimum sda setup ti me minimum sda hold time 0 t low - 4 system clocks or 1 system clock + s/w delay* 3 system clocks 1 11 system clocks 12 system clocks *note: setup time for ack bit transmissions and th e msb of all data transfers. the s/w delay occurs between the time smb0dat or ack is writ ten and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero. scl timer source overflows scl high timeout t low t high
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 194 rev. 1.3 sfr definition 17.1. smb0cf: smbus clock/configuration bit7: ensmb: smbus enable. this bit enables/disables the smbus interface. when enabled, the interface constantly mon- itors the sda and scl pins. 0: smbus interface disabled. 1: smbus interface enabled. bit6: inh: smbus slave inhibit. when this bit is set to logic 1, the smbus does not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 0: smbus slave mode enabled. 1: smbus slave mode inhibited. bit5: busy: smbus busy indicator. this bit is set to logic 1 by hardware when a tran sfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. bit4: exthold: smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. bit3: smbtoe: smbus scl ti meout detection enable. this bit enables scl low timeout detection. if set to logic 1, the sm bus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbu s communication. bit2: smbfte: smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 smbus cl ock source periods. bits1?0: smbcs1-smbcs0: smbu s clock source selection. these two bits select the smbus clock source , which is used to generate the smbus bit rate. the selected device should be configured according to equation 17.1. r/w r/w r r/w r/w r/w r/w r/w reset value ensmb inh busy exthold smbtoe smbfte smbcs1 smbcs0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc1 smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow
rev. 1.3 195 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 17.4.2. smb0cn control register smb0cn is used to control the interface and to provide status information (see sfr definition 17.2 ). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to ju mp to service routines. master and txmode indi cate the master/slave state and transmit/receive modes, respectively. sta and sto indicate that a start and/or stop has been detected or generated since the last smbus in terrupt. sta and sto are also used to generate start and stop conditions when operating as a mas - ter. writing a ?1? to sta will caus e the smbus interface to enter master mode and generate a st art when the bus becomes free (sta is not cleared by hardware after the start is generated). writing a ?1? to sto while in master mode will cause th e interface to generate a stop an d end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received on the la st ack cycle. ackrq is set each time a byte is received, indicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if so ftware does not write the ack bit before clearing si. sda will reflec t the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave ad dress is not acknowledged, further slave events will be ignored until th e next start is detected. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condi - tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see ta b l e 17.3 for more details. important note about the si bit: the smbus interface is st alled while si is set; th us scl is held low, and the bus is stalled until software clears si. ta b l e 17.3 lists all sources for hardware changes to the smb0cn bits. refer to ta b l e 17.4 for smbus sta - tus decoding using the smb0cn register.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 196 rev. 1.3 sfr definition 17.2. smb0cn: smbus control bit7: master: smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. bit6: txmode: smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. bit5: sta: smbus start flag. write: 0: no start generated. 1: when operating as a master, a start condition is transmitted if the bus is free (if the bus is not free, the start is transmitted after a stop is received or a timeout is detected). if sta is set by software as an active master, a repeated start will be generated after the next ack cycle. read: 0: no start or repeated start detected. 1: start or repeated start detected. bit4: sto: smbus stop flag. write: 0: no stop condition is transmitted. 1: setting sto to logic 1 causes a stop condition to be transmitted after the next ack cycle. when the stop condition is generated, hardware clears sto to logic 0. if both sta and sto are set, a stop condition is transmitted followed by a start condition. read: 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). bit3: ackrq: smbus ac knowledge request this read-only bit is set to logic 1 when the smbus has received a byte and needs the ack bit to be written with the correct ack response value. bit2: arblost: smbus arbitration lost indicator. this read-only bit is set to logic 1 when the smbus loses arbitration while operating as a transmitter. a lost arbitration while a slave indicates a bus error condition. bit1: ack: smbus acknowledge flag. this bit defines the out-going ack level and re cords incoming ack leve ls. it should be writ- ten each time a byte is received (when ackr q=1), or read after each byte is transmitted. 0: a "not acknowledge" has been received (if in transmitter mo de) or will be transmitted (if in receiver mode). 1: an "acknowledge" has been re ceived (if in transmitter mode) or will be transmitted (if in receiver mode). bit0: si: smbus interrupt flag. this bit is set by hardware under the conditions listed in table 17.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. r r r/w r/w r r r/w r/w reset value master txmode sta sto ackrq arblost ack si 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xc0
rev. 1.3 197 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d table 17.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master ? a start is generated. ? a stop is generated. ? arbitration is lost. txmode ? start is generated. ? smb0dat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smb0dat is not written before the start of an smbus frame. sta ? a start followed by an address byte is received. ? must be cleared by software. sto ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ackrq ? a byte has been received and an ack response value is needed. ? after each ack cycle. arblost ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low while attempting to gener - ate a stop or repeated start condition. ? sda is sensed low while transmitting a ?1? (excluding ack bits). ? each time si is cleared. ack ? the incoming ack value is low (acknowl - edge). ? the incoming ack value is high (not acknowledge). si ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/ nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 198 rev. 1.3 17.4.3. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, a s the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted out msb first. after a byte has been received, the first bit of received d ata is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi - tration, the transition from master transmitter to slave r eceiver is made with the correct data or address in smb0dat. sfr definition 17.3. smb0dat: smbus data 17.5. smbus transfer modes the smbus interface may be configured to operate as master and /or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames; however, note that the inte rrupt is generated before the ack cycle when operat - ing as a receiver, and after the ack cycle when operating as a transmitter. 17.5.1. master transmitter mode serial data is transmitted on sda while the serial cl ock is output on scl. the smbus interface generates the start condition and transmits the first byte cont aining the address of the target slave and the data direction bit. in this case the data direction bit (r/w) will be logic 0 (write). the master then transmits o ne or more bytes of serial data. after each byte is transmitted, an acknowled ge bit is generated by the slave. the transfer is en ded when the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written following a master transmitter interrupt. figure 17.5 shows a typical master transmitter sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that the ?data byte transferred? interrupts occur after the ack cycle in this mode. bits7-0: smb0dat: smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial inter- face or a byte that has just been received on the smbus serial interface. the cpu can read from or write to this register whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu should not atte mpt to access this register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc2
rev. 1.3 199 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 17.5. typical mast er transmitter sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 200 rev. 1.3 17.5.2. master receiver mode serial data is received on sda while the serial clock is output on scl. the smbus interface generates the start condition and transmits the first byte containing the address of the target slave and the data direc - tion bit. in this case the data direction bit (r/w) will be logic 1 (read). serial data is then received from the slave o n sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. after each byte is received, ackrq is set to ?1? and an interrupt is generated. software must write the ack bit (smb0cn.1) to define the outgoing acknow ledge value (note: writing a ?1? to the ack bit gen - erates an ack; writing a ?0? generates a nack). software should write a ?0? to the ack bit after the last by te is received, to transmit a na ck. the interface exits master receiver mode after the sto bit is set and a stop is generated. note that the interface will switch to master tr ansmitter mode if smb0dat is written while an active master receiver. figure 17.6 shows a typical master rece iv er sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. figure 17.6. typical m aster receiver sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt
rev. 1.3 201 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 17.5.3. slave receiver mode serial data is received on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direction bit (write in this case) is received. upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the received slave addre ss is ignored, slave interr upts will be inhibited until the next start is detected. if the received slave addr ess is acknowledged, zero or more data bytes are received. software must write the ack bit after each received byte to ack or nack the received byte. the interface exits slave receiver mode after receiv ing a stop. note that the in terface will switch to slave transmitter mode if smb0dat is written while an active slave receiver. figure 17.7 shows a typical slave receiver sequence. two received data bytes are shown, though any number of bytes may be received. notice th at the ?data byte transferred? interrupts occur before the ack cycle in this mode. figure 17.7. typical sl ave receiver sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 202 rev. 1.3 17.5.4. slave transmitter mode serial data is transmitted on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to re ceive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. upon entering slave transmitter mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the received slave address is ignored, slave interrupts will be inhi bited until a start is detect ed. if the received slave ad dress is ack nowledged, data should be written to smb0dat to be transmitted. the interface enters slave transmitter mode, and trans - mits one or more bytes of data. after each byte is tr an smitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowledge bit is a nack, smb0dat should not be written to before si is cleared (note: an error condition may be gener - ated if smb0dat is written followi ng a received nack while in slave transmitter mode). the interface exits slave transmitter mode after receiving a stop. note that the interface will switch to slave receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 17.8 shows a typical slave transmitter sequence. two transmitted data bytes ar e shown , though any number of bytes may be trans - mitted. notice that the ?data byte tr ansferred? interrupts occur after the ack cycle in this mode. figure 17.8. typical sl ave transmitter sequence 17.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. in the table below, status vector refers to the four upper bits of smb0cn : master, txmode, sta, and sto. note that the shown response options are only the typical response s; application-specific pr ocedures are allowed as long as they conform to the smbus specification. hi ghlighted responses are allowed but do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt
rev. 1.3 203 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d table 17.4. smbus status decoding mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0da t. 0 0 x 1100 000 a master data or address byte was t ransmitted; nack received. set sta to restart transfer. 1 0 x abort transfer. 0 1 x 001 a master data or address byte was t ransmitted; ack received. load next data byte into smb0da t. 0 0 x end transfer with stop. 0 1 x end transfer with stop and st art another transfer. 1 1 x send repeated start. 1 0 x switch to master receiver mode (clear si without writ - ing new data to smb0dat). 0 0 x master receiver 1000 1 0 x a master data byte was received; ack r equested. acknowledge received byte; read smb0da t. 0 0 1 send nack to indicate last b yte, and send stop. 0 1 0 send nack to indicate last byte, and send stop fol - lowed by start. 1 1 0 send ack followed by re peated start. 1 0 1 send nack to indicate last byte, a nd send repeated start. 1 0 0 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 send nack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 0
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 204 rev. 1.3 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expect - ing stop condition). 0 0 x 001 a slave byte was transmitted; ack received. load smb0dat with next dat a byte to transmit. 0 0 x 01x a slave byte was transmitted; er ror detected. no action required (expect - ing master to end transfer). 0 0 x 0101 0 x x an illegal stop or bus error was de tected while a slave transmis - sion was in progress. clear sto. 0 0 x slave receiver 0010 10x a slave address was received; ack r equested. acknowledge received ad dress. 0 0 1 do not acknowledge re ceived address. 0 0 0 11x lost arbitration as master; slave ad dress received; ack requested. acknowledge received ad dress. 0 0 1 do not acknowledge re ceived address. 0 0 0 reschedule failed transfer; do not acknowledge received address. 1 0 0 0010 0 1 x lost arbitration while attempting a r epeated start. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 0001 11 x lost arbitration while attempting a st op. no action required (transfer co mplete/aborted). 0 0 0 00x a stop was detected while ad dressed as a slave transmitter or slave receiver. clear sto. 0 0 x 01x lost arbitration due to a detected st op. abort transfer. 0 0 x reschedule failed transfer. 1 0 x 0000 10 x a slave byte was received; ack r equested. acknowledge received byte; read smb0da t. 0 0 1 do not acknowledge re ceived byte. 0 0 0 11x lost arbitration while transmitting a da ta byte as master. abort failed transfer. 0 0 0 reschedule failed transfer. 1 0 0 table 17.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack
rev. 1.3 205 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 18. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enh anced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?18.1. enhanced baud rate generation? on page 206 ). received data buffering allows uart0 to start reception of a second incoming data byte before software has finished reading the previous dat a byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 18.1. uart0 block diagram uart0 baud rate generator ri0 scon ri0 ti0 rb80 tb80 ren0 mce0 s0mode tx control tx clock send sbuf0 (tx shift) start data write to sbuf0 crossbar tx0 shift zero detector tx irq set qd clr stop bit tb80 sfr bus serial port interrupt ti0 port i/o rx control start rx clock load sbuf0 shift 0x1ff rb80 rx irq input shift register (9 bits) load sbuf0 read sbuf0 sfr bus crossbar rx0 sbuf0 (rx latch)
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 206 rev. 1.3 18.1. enhanced baud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl 1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 18.2 ), which is not user-accessible. both tx and rx timer overflows are divided by two to generate the tx and rx baud r ates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to b egin any time a start is detected, independent of the tx timer state. figure 18.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?21.1.3. mode 2: 8-bit counter/ timer with auto-reload? on page 237 ). the timer 1 reload value should be set so that overflows will occur at two times the desired uart b aud rate frequency. note that timer 1 may be clocked by one of six sources: sysclk, sysclk / 4, sysclk / 12, sysclk / 48, the external oscillator clock / 8, or an exter - nal input t1. for any given timer 1 clock source, the uart0 baud rate is determined by equation 18.1 . equation 18.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as described in section ?21. timers? on page 235 . a quick reference for typical baud rates using the internal oscillator is given in ta b l e 18.1 . note that the internal oscillator may still generate the system clock if an external oscillator is dr iving timer 1. 18.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown below. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart uartbaudrate t 1 clk 256 t 1 h ? ?? ?
rev. 1.3 207 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 18.3. uart interconnect diagram 18.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit . data are transmitted lsb first from the tx0 pin a nd received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins when softwa r e writes a data byte to the sbuf 0 register. the ti0 transmit inter - rupt flag (scon0.1) is set at the end of the transmi ssion ( the beginning of the stop-bit time). data recep - tion can begin any time after the ren0 receive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the dat a byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over - run, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data bits ar e lost. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditions are not met, sbu f0 and rb80 will not be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. figure 18.4. 8-bit u art timing diagram or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 208 rev. 1.3 18.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma - ble ninth data bit, and a stop bit. th e state of the ninth transmit data bit is determined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg - ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit g oes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a d ata byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enable bit (scon0.4) is set to ?1?. after the stop bit is received, the da ta byte will be loaded in to the sbuf0 receive register if the following conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the st ate of the ninth data bit is unimportant). if these cond itions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to ?1?. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to ?1?. a uart 0 interrupt will occur if enabled when either ti0 or ri0 is set to ?1?. figure 18.5. 9-bit u art timing diagram 18.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor con figures its uart such that when a stop bit is received, the uart will gener ate an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address byte has been received. in the uart interrupt ha ndler, software will compare the received address with the slave's own assigned 8-bit address. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addres sed slave resets its mce0 bit to ignore all transmis - sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and /or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
rev. 1.3 209 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 18.6. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 210 rev. 1.3 sfr definition 18.1. scon0: serial port 0 control bit7: s0mode: serial port 0 operation mode. this bit selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. bit6: unused. read = 1b. write = don?t care. bit5: mce0: multiprocessor communication enable. the function of this bit is dependent on the serial port 0 operation mode. s0mode = 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. s0mode = 1: multiprocesso r communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is generated only when the ninth bit is logic 1. bit4: ren0: receive enable. this bit enables/disables the uart receiver. 0: uart0 reception disabled. 1: uart0 reception enabled. bit3: tb80: ninth transmission bit. the logic level of this bit will be assigned to t he ninth transmission bit in 9-bit uart mode. it is not used in 8-bit uart mode. set or cleared by software as required. bit2: rb80: ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. bit1: ti0: transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8-bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. bit0: ri0: receive interrupt flag. set to ?1? by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enab led, setting this bit to ?1? causes the cpu to vector to the uart0 interrup t service routine. this bit must be cleared manually by soft- ware. r/w r r/w r/w r/w r/w r/w r/w reset value s0mode - mce0 ren0 tb80 rb80 ti0 ri0 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x98
rev. 1.3 211 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 18.2. sbuf0: serial (uart0 ) por t data buffer bits7?0: sbuf0[7:0]: serial da ta buffer bits 7?0 (msb-lsb) this sfr accesses two registers; a transmit sh ift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmis- sion. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the con- tents of the receive latch. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x99
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 212 rev. 1.3 table 18.1. timer settings for standard baud ra tes using the internal oscillator target baud rate (bps) actual baud rate (bps) baud rate error oscillator divide factor timer clock source sca1-sca0 (pre-scale select* t1m* timer 1 reload value (hex) sysclk = 12 mhz 230400 23076 9 0.16% 52 sysclk xx 1 0xe6 115200 115385 0.16% 104 sysclk xx 1 0xcc 57600 57692 0.16% 20 8 sysclk xx 1 0x98 28800 28846 0.16% 41 6 sysclk xx 1 0x30 14400 14423 0.16% 832 sysclk / 4 01 0 0x98 9600 9615 0.16% 1248 sysclk / 4 01 0 0x64 2400 2404 0.16% 4992 sysclk / 12 00 0 0x30 1200 1202 0.16% 9984 sysclk / 48 10 0 0x98 sysclk = 24 mhz 230400 230769 0.16% 104 sysclk xx 1 0xcc 115200 115385 0.16% 208 sysclk xx 1 0x98 57600 57692 0.16% 41 6 sysclk xx 1 0x30 28800 28846 0.16% 832 sysclk / 4 01 0 0x98 14400 14423 0.1 6% 1664 sysclk / 4 01 0 0x30 9600 9615 0.16% 2496 sysclk / 12 00 0 0x98 2400 2404 0.16% 9984 sysclk / 48 10 0 0x98 1200 1202 0.16% 19968 sysclk / 48 10 0 0x30 sysclk = 48 mhz 230400 230769 0 .16% 208 sysclk xx 1 0x98 115200 115385 0.16% 416 sysclk xx 1 0x30 57600 57692 0.16% 832 sysclk / 4 01 0 0x98 28800 28846 0.1 6% 1664 sysclk / 4 01 0 0x30 14400 14388 0.0 8% 3336 sysclk / 12 00 0 0x75 9600 9615 0.16% 4992 sysclk / 12 00 0 0x30 2400 2404 0.16% 19968 sysclk / 48 10 0 0x30 x = don?t care *note: sca1-sca0 and t1m define the timer clock source. bi t definitions for these values can be found in section 21.1 .
rev. 1.3 213 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 19. uart1 (c8051f340/ 1/4/5/8/a/b/c only) uart1 is an asynchronous, full duplex serial port offeri ng a variety of data formatting options. a dedicated baud rate generator with a 16-bit timer and select able prescaler is included, which can generate a wide range of baud rates (details in section ?19.1. baud rate generator? on page 214 ). a received data fifo allows uart1 to receive up to three data bytes before data is lost and an overflow occurs. uart1 has six associated sfrs. three are used for the baud rate generator (sbcon1, sbrlh1, and sbrl l1), two are used for data formatting, control, and status functions (scon1, smod1), and one is used to send and receive data (sbuf1). the single sbuf1 location provides access to both the transmit holding register and the receive fifo. writes to sbuf1 always access the transmit holding register. reads of sbuf1 always access the first byte of the receive fifo; it is not possible to read data from the transmit holding register. with uart1 interrupts enabled, an interrupt is generated each time a transmit is completed (ti1 is set in scon1), or a data byte has been received (ri1 is set in scon1). the uart1 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart1 interrupt (transmit complete or receive complete). note that if additional bytes are available in the receive fifo, the ri1 bit cannot be cleared by software. figure 19.1. uart1 block diagram sbuf1 tx holding register rx fifo (3 deep) tx logic rx logic write to sbuf1 read of sbuf1 tx1 rx1 smod1 mce1 s1pt1 s1pt0 pe1 s1dl1 s1dl0 xbe1 sbl1 data formatting scon1 ovr1 perr1 thre1 ren1 tbx1 rbx1 ti1 ri1 control / status uart1 interrupt timer (16-bit) pre-scaler (1, 4, 12, 48) sysclk sbrlh1 sbrll1 overflow sbcon1 sb1run sb1ps1 sb1ps0 en baud rate generator
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 214 rev. 1.3 19.1. baud rate generator the uart1 baud rate is generated by a dedicated 16-bi t timer which runs from the controller?s core clock (sysclk), and has prescaler options of 1, 4, 12, or 48. the timer and prescaler options combined allow for a wide selection of baud rates over many sysclk frequencies. the baud rate generator is configured using th re e registers: sbcon1, sbrlh1, and sbrll1. the uart1 baud rate generator co ntrol register (sbcon1, sfr definition 19.4 ) enables or disables the baud rate generator, and selects the prescaler value for the timer. the baud rate generator must be e nabled for uart1 to function. registers sbrlh1 and sbrll1 contain a 16-bit reload value for the dedi - cated 16-bit timer. the internal timer counts up from the reload value on every clock tick. on timer over - flows (0xffff to 0x0000), the timer is reloaded. fo r re liable uart operation, it is recommended that the uart baud rate is not configured for baud rates faster than sysclk/16. the bau d rate for uart1 is defined in equation 19.1 . equation 19.1. uart1 baud rate a quick reference for typical baud rates and system clock frequencies is given in ta b l e 19.1 . table 19.1. baud rate generator settings for standard baud rates target baud rate (bps) actual baud rate (bps) baud rate error oscillator divide factor sb1ps[1:0] (prescaler bits) reload value in sbrlh1:sbrll1 sysclk = 12 mhz 230400 230769 0.16% 52 11 0xffe6 115200 115385 0.16% 104 11 0xffcc 57600 57692 0.16% 208 11 0xff98 28800 28846 0.16% 416 11 0xff30 14400 14388 0.08% 834 11 0xfe5f 9600 9600 0.0% 1250 11 0xfd8f 2400 2400 0.0% 5000 11 0xf63c 1200 1200 0.0% 10000 11 0xec78 sysclk = 24 mhz 230400 230769 0.16% 104 11 0xffcc 115200 115385 0.16% 208 11 0xff98 57600 57692 0.16% 416 11 0xff30 28800 28777 0.08% 834 11 0xfe5f 14400 14406 0.04% 1666 11 0xfcbf 9600 9600 0.0% 2500 11 0xfb1e 2400 2400 0.0% 10000 11 0xec78 1200 1200 0.0% 20000 11 0xd8f0 sysclk = 48 mhz 230400 230769 0.16% 208 11 0xff98 115200 115385 0.16% 416 11 0xff30 57600 57554 0.08% 834 11 0xfe5f 28800 28812 0.04% 1666 11 0xfcbf 14400 14397 0.02% 3334 11 0xf97d 9600 9600 0.0% 5000 11 0xf63c 2400 2400 0.0% 20000 11 0xd8f0 1200 1200 0.0% 40000 11 0xb1e0 baud rate sysclk 65536 (sbrlh1:sbrll1) ? ?? ----------------------------------------------------------- ---------------- 1 2 -- - ? 1 prescaler ----------- ---------- - ? =
rev. 1.3 215 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 19.2. data format uart1 has a number of available options for data format ting. data transfers begin with a start bit (logic low), followed by the data bits (sent lsb-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). the data length is variable between 5 and 8 bits. a parity bit can be appended to the data, and automatically generated and detected by hardware for even, odd, mark, or space parity. the stop bit length is selectable between short (1 bit time) and long (1.5 or 2 bit times), and a multi-processor com - munication mode is available for implementing networ ked uart buses. all of the data formatting options can be configured using the smod1 register, shown in sfr definition 19.2 . figure 19.2 shows the timing for a uart1 transaction without parity or an extra bit enabled. figure 19.3 shows the timing for a uart1 transaction with parity enabled (pe1 = 1). figure 19.4 is an example of a uart1 transaction when the extra bit is enabled (xbe1 = 1). note that the extra bit feature is no t a vailable when parity is enabled, and the second stop bit is only an option for data lengths of 6, 7, or 8 bits. figure 19.2. uart1 timing wit hout parity or extra bit figure 19.3. uart1 timing with parity figure 19.4. uart1 ti mi ng with extra bit d 1 d 0 d n-2 d n-1 start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional d 1 d 0 d n-2 d n-1 parity start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional d 1 d 0 d n-2 d n-1 extra start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 216 rev. 1.3 19.3. configuration and operation uart1 provides standard asynchronous, full duplex communication. it can operate in a point-to-point serial communications application, or as a node on a multi-processor serial interface. to operate in a point-to-point application, where t here are only two devices on the serial bus, the mce1 bit in smod1 should be cleared to ?0?. for operation as part of a multi-processor communications bus, the mce1 and xbe1 bits should both be set to ?1?. in both types of applications, data is tr ansmitted from the microcon - troller on the tx1 pin, and received on the rx1 pin. th e tx1 and rx1 pins are configured using the cross - bar and the port i/o registers, as detailed in section ?15. port input/output? on page 142 . in typical uart communications, the transmit (tx) outp ut of one device is connec ted to the receive (rx) input of the other device, either directly or through a bus transceiver, as shown in figure 19.5 . figure 19.5. typical uart interconnect diagram 19.3.1. data transmission data transmission is double-buffered, and begins when software writes a data byte to the sbuf1 register. writing to sbuf1 places data in the transmit holdin g register, and the transmit holding register empty flag (thre1) will be cleared to ?0?. if the uarts shift register is empt y (i.e., no transmissi on is in progress) the data will be placed in the shift register, and the thre1 bit will be set to ?1?. if a transmission is in prog - ress, the data will remain in the t ransmit holding register until the current transmission is complete. the ti1 transmit interrupt flag (scon1.1) will be set at the end of any transmission (the beginning of the stop-bit time). if enabled, an inte rrupt will occur when ti1 is set. if the extra bit function is enabled (xbe1 = ?1?) and the parity function is disabled (pe1 = ?0?), the value of the tbx1 (scon1.3) bit will be sent in the extra bit po sition. when the parity function is enabled (pe1 = ?1?), hardware will generate the parity bit according to the selected pari ty type (selected with s1pt[1:0]), and append it to the data field. note: when parity is enabled, the extra bit function is not available. 19.3.2. data reception data reception can begin any time after the ren1 receive enable bit (scon1.4) is set to logic 1. after the stop bit is received, the data byte w ill be stored in the receive fifo if the following condit ions are met: the receive fifo (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. in the event that the receive fifo is full, the incoming byte w ill be lost, and a receive fi fo overrun error will be generated (ovr1 in register scon 1 will be set to logic 1). if the stop bit(s) were logic 0, the incoming data will not be stor ed in the receive fifo. if the reception conditions ar e met, the data is stored in the receive fifo, and the ri1 flag will be set. note: when mce1 = ?1?, ri1 will only be set if the extra bit was equal to ?1?. data can be read from the receive fifo by reading the sbuf1 register. the sbuf1 register represents the oldest byte in the fifo. after sbuf1 is read, the next byte in the fifo is immediately loaded into sbuf1, and or rs-232 c8051fxxx rs-232 level translator tx rx c8051fxxx rx tx mcu rx tx pc com port
rev. 1.3 217 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d space is made available in the fifo for another incoming byte. if enabled, an interrupt will occur when ri1 is set. ri1 can only be cleared to '0' by software w hen there is no more information in the fifo. the rec - ommended procedure to empty the fifo contents is as follows: 1. clear ri1 to '0'. 2. read sbuf1. 3. check ri1, and repeat at step 1 if ri1 is set to '1'. ? if the extra bit function is enabled (xbe1 = ?1?) and the parity function is disabled (pe1 = ?0?), the extra bit for the oldest byte in the fifo can be read from th e rbx1 bit (scon1.2). if the extra bit function is not enabled, the value of the stop bit fo r the oldest fifo byte will be pres ented in rbx1. when the parity func - tion is enabled (pe1 = ?1?), hardwa re will check the received p arity bi t against the selected parity type (selected with s1pt[1:0]) when receiving data. if a byte with parity error is rece ived, the perr1 flag will be set to ?1?. this flag must be cleared by software. note: when parity is enabled, th e extra bit function is not available. 19.3.3. multiprocessor communications uart1 supports multiprocessor communication between a master processor and one or more slave pro - cessors by special use of the extra data bit. when a master processor wants to transmit to one or more slaves, it fir st sends an address byte to select the target (s). an address byte differs from a data byte in that its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0. setting the mce1 bit (smod1.7) of a slave processor c onfig ures its uart such that when a stop bit is received, the uart will generate an interrupt only if the extra bit is logic 1 (rbx1 = 1) signifying an address byte has been rece ived. in the uart interrupt handler, software w ill compare the received address with the slave's own assigned address. if th e addresses match, the slave will clear its mce1 bit to enable interrupts on the reception of the following da ta byte(s). slaves that we ren't addressed leave their mce1 bits set and do not generate interrupts on the rece ption of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce1 bit to ignore all trans - missions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and /or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be i mplemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 218 rev. 1.3 figure 19.6. uart multi-processor mode interconnect diagram sfr definition 19.1. scon1: uart1 control bit7: ovr1: receive fifo overrun flag. this bit is used to indicate a receive fifo overrun condition. 0: receive fifo overrun has not occurred. 1: receive fifo overrun has occurred (an incoming character was discarded due to a full fifo). this bit must be cleared to ?0? by software. bit6: perr1: parity error flag. when parity is enabled, this bit is used to indi cate that a parity error has occurred. it is set to ?1? when the parity of the oldest byte in the fifo does not match the selected parity type. 0: parity error has not occurred. 1: parity error has occurred. this bit must be cleared to ?0? by software. bit5: thre1: transmit holding register empty flag. 0: transmit holding register not empty - do not write to sbuf1. 1: transmit holding register empty - it is safe to write to sbuf1. bit4: ren1: receive enable. this bit enables/disables the ua rt receiver. when disabled, by tes can still be read from the receive fifo. 0: uart1 reception disabled. 1: uart1 reception enabled. bit3: tbx1: extra transmission bit. the logic level of this bit will be assigned to the extra transmission bit when xbe1 is set to ?1?. this bit is not used when parity is enabled. bit2: rbx1: extra receive bit. rbx1 is assigned the value of t he extra bit when xbe1 is set to ?1?. if xbe1 is cleared to ?0?, rbx1 will be assigned the logic level of the first stop bit. this bit is not valid when parity is enabled. bit1: ti1: transmit interrupt flag. set to a ?1? by hardware after data has been transmitted, at the beginning of the stop bit. when the uart1 interrupt is enabled, setting this bit causes the cpu to vector to the uart1 interrupt service routine. this bit must be cleared manually by software. bit0: ri1: receive interrupt flag. set to ?1? by hardware when a byte of data has been received by uart1 (set at the stop bit sampling time). when the uart1 interrupt is enab led, setting this bit to ?1? causes the cpu to vector to the uart1 interrup t service routine. this bit must be cleared manually by soft- ware. note that ri1 will remain set to '1' as long as there is still data in the uart fifo. after the last byte has been shifted from t he fifo to sbuf1, ri1 can be cleared. r/w r/w r r/w r/w r/w r/w r/w reset value ovr1 perr1 thre1 ren1 tbx1 rbx1 ti1 ri1 00100000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd2
rev. 1.3 219 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 19.2. smod1: uart1 mode bit7: mce1: multiprocessor communication enable. 0: ri will be activated if stop bit(s) are ?1?. 1: ri will be activated if stop bit(s) and extra bit are ?1? (e xtra bit must be enabled using xbe1). note: this function is not availabl e when hardware parity is enabled. bits6?5: s1pt[1:0]: parity type. 00: odd 01: even 10: mark 11: space bit4: pe1: parity enable. this bit activates hardware pa rity generation and checking. th e parity type is selected by bits s1pt1-0 when parity is enabled. 0: hardware parity is disabled. 1: hardware parity is enabled. bits3?2: s1dl[1:0]: data length. 00: 5-bit data 01: 6-bit data 10: 7-bit data 11: 8-bit data bit1: xbe1: extra bit enable when enabled, the value of tbx1 will be appended to the data field. 0: extra bit disabled. 1: extra bit enabled. bit0: sbl1: stop bit length 0: short - stop bit is active for one bit time. 1: long - stop bit is active for two bit times (dat a length = 6, 7, or 8 bits), or 1.5 bit times (data length = 5 bits). r/w r/w r/w r/w r/w r/w r/w r/w reset value mce1 s1pt1 s1pt0 pe1 s1dl1 s1dl0 xbe1 sbl1 00001100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe5
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 220 rev. 1.3 sfr definition 19.3. sbuf1: uart1 data buffer sfr definition 19.4. sbcon1: uart1 baud rate generator control bits7?0: sbuf1[7:0]: serial da ta buffer bits 7?0 (msb-lsb) this sfr is used to both send data from the uart and to read received data from the uart1 receive fifo. write: writing a byte to sbuf1 initiates the tr ansmission. when data is written to sbuf1, it first goes to the transmit holding register, wher e it is held for serial transmission. when the transmit shift register is available, data is transferred into the shift register, and sbuf1 may be written again. read: reading sbuf1 retrieves data from the receive fifo. when read, the oldest byte in the receive fifo is returned, and removed from the fifo. up to three bytes may be held in the fifo. if there are ad ditional bytes available in the fi fo, the ri1 bit will remain at logic ?1?, even after being cleared by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd3 bit7: reserved: read = 0b; must write 0b. bit6: sb1run: baud ra te generator enable. 0: baud rate genera tor is disabled. uart1 will not function. 1: baud rate generator is enabled. bits5?2: reserved: read = 0 000b; must write 0000b. bits1?0: sb1ps[1:0]: baud ra te prescaler select. 00: prescaler = 12 01: prescaler = 4 10: prescaler = 48 11: prescaler = 1 r/w r/w r/w r/w r/w r/w r/w r/w reset value reserved sb1run reserved reserved reserved rese rved sb1ps1 sb1ps0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xac
rev. 1.3 221 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 19.5. sbrlh1: uart1 baud rate generator high byte sfr definition 19.6. sbrll1: uart1 baud rate generator low byte bits7?0: sbrlh1[7:0]: high byte of relo ad value for uart1 baud rate generator. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb5 bits7?0: sbrll1[7:0]: low byte of reload value for uart1 baud rate generator. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb4
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 222 rev. 1.3 20. enhanced serial peri pheral interface (spi0) the enhanced serial peripheral interface (spi0) prov ides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave devi ce in both 3-wire or 4-wire modes, and supports mul - tiple masters and slaves on a single spi bus. the slav e -select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master m ode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen - eral purpose port i/o pins can be used to sele ct multiple slave devices in master mode. figure 20.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien
rev. 1.3 223 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 20.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 20.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat - ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 20.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output fr om a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat - ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not selected. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 20.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mas ter device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen - erates this signal when operating as a master. the sck s ignal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 20.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave dev ice, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point-to-point communi cation between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-mast er mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of th e nss signal disables t he master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 determines what logic level the nss pin will output. this configuration should only be used wh en operating spi0 as a master device. see figure 20.2 , figure 20.3 , and figure 20.4 for typical connection diagra m s of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ? 15. port input/output ? on page 142 for general purpose port i/o and crossbar information.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 224 rev. 1.3 20.2. spi0 master mode operation a spi master device initiate s all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cfg.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the rece ive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of thr ee different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, n ss is an input to the device, and is used to disable the master spi0 when another maste r is accessing the bus. when nss is pulled low in this mode, msten (spi0cfg.6) and spien (spi0cn.0) are set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an inte rrupt if e nabled. spi0 must be manually re-enabled in software under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas - ter mode, slave devices can be addressed individua lly (if ne eded) using general-purpose i/o pins. figure 20.2 shows a connection diagram between two mas ter devices in mu ltiple-master mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 20.3 shows a connection diagram between a master device in 3- wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0c n.3) = 1. in this mode, nss is configured as an output pin, and can be used as a slave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit n ssmd0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 20.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices.
rev. 1.3 225 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 20.2. multiple-master mode connect ion diagram figure 20.3. 3-wire single master and slave mode connection diagram figure 20.4. 4-wire single master mo de and slave mode connection diagram master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 226 rev. 1.3 20.3. spi0 slave mode operation when spi0 is enabled and not configured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig - nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted through the shift reg - ister, the spif flag is set to logic 1, and the byte is co pied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are dou - ble-buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be tr ansferred into the shift register. w hen the shift register already con - tains data, the spi will load the shift register w ith the transmit buffer?s contents after the last sck edge of the next (or curr ent) spi transfer. when configured as a slave, spi0 can be configured fo r 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabled when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of n ss. note that the nss sig - nal must be driven low at least 2 system clocks before th e first active edge of sck for each byte transfer. figure 20.4 shows a connection diagram between two slave de vices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. the bit counter can only be reset by disabling and re-enabling spi0 with the spien bit. figure 20.3 shows a connection diagram between a slave device in 3-wire slave mode and a master device. 20.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: note that all of the following bits must be cleared by software. 1. the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. 2. the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the transmi t buffer will not be written.this flag can occur in all spi0 modes. 3. the mode fault flag modf (spi0cn.5) is set to logic 1 when spi0 is configured as a master, a nd for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logi c 0 to disable spi0 and allow another master device to access the bus. 4. the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost.
rev. 1.3 227 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 20.5. serial clock timing four combinations of serial clock p hase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be conf igured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 20.5 . for slave mode, the clock and data relationships are shown in figure 20.6 and figure 20.7 . the spi0 clock rate register (spi0ckr) a s shown in sfr definition 20.3 controls the master mode serial clock frequency. this register is ignored when o perating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock freque ncy, provided that the mast er issues sck, nss (in 4-wire slave mode), and the serial input data synchron ously with the slave?s syst em clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master issu es sck, nss, and the serial input data synchronously with the slave?s system clock. figure 20.5. master mode data/clock timing sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode)
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 228 rev. 1.3 figure 20.6. slave mode data /clock timing (ckpha = 0) figure 20.7. slave mode data /clock timing (ckpha = 1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi
rev. 1.3 229 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 20.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data re gister, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. sfr definition 20.1. spi0cfg: spi0 configuration bit 7: spibsy: spi busy (read only). this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). bit 6: msten: master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. bit 5: ckpha: spi0 clock phase. this bit controls the spi0 clock phase. 0: data centered on first edge of sck period.* 1: data centered on second edge of sck period.* bit 4: ckpol: spi0 clock polarity. this bit controls the spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. bit 3: slvsel: slave selected flag (read only). this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but ra ther a de-glitched version of the pin input. bit 2: nssin: nss instantaneous pin input (read only). this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. bit 1: srmt: shift register empty (valid in slave mode, read only). this bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to r ead from the transmit buffer or write to the receive buffer. it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. note: srmt = 1 when in master mode. bit 0: rxbmt: receive buffer empty (valid in slave mode, read only). this bit will be set to logic 1 when the receiv e buffer has be en read and contains no new information. if there is new information availabl e in the receive buffer that has not been read, this bit will return to logic 0. note: rxbmt = 1 when in master mode. *note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maxi mum settling time fo r the slave device. see table 20.1 for timing parameters. r r/w r/w r/w r r r r reset value spibsy msten ckpha ckpol slvsel nssin srmt rxbmt 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa1
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 230 rev. 1.3 sfr definition 20.2. spi0cn: spi0 control bit 7: spif: spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data trans fer. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt service routine. this bit is not automatically cleared by hardware. it must be cleared by software. bit 6: wcol: write collision flag. this bit is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occu rs, the write to spi0dat will be ignored, and the tran smit buffer will not be written. this flag can occur in a ll spi0 modes. it must be cleared by software. bit 5: modf: mode fault flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when a master mode collision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). this bit is not auto- matically cleared by hardware. it must be cleared by software. bit 4: rxovrn: receive overrun flag (slave mode only). this bit is set to logic 1 by hardware (and ge nerates a spi0 interrupt) when the receive buf- fer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the spi0 shift register. this bit is not automatically cleare d by hardware. it must be cleared by software. bits 3?2: nssmd1?nssmd0: slave select mode. selects between the following nss operation modes: (see section ?20.2. spi0 master mode operation? on page 224 and section ?20.3. spi0 slave mode operation? on page 226 ). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (defau lt). nss is always an input to the device. 1x: 4-wire single-master mode. nss signal is mapped as an output fr om the device and will assume the value of nssmd0. bit 1: txbmt: transmit buffer empty. this bit will be set to logic 0 when new data has been written to th e transmit buffer. when data in the transmit buffer is tr ansferred to the spi shif t register, this bit will be set to logic 1, indicating that it is safe to writ e a new byte to the transmit buffer. bit 0: spien: spi0 enable. this bit enables/disables the spi. 0: spi disabled. 1: spi enabled. r/wr/wr/wr/wr/wr/w r r/wreset value spif wcol modf rxovrn nssmd1 nssmd0 txbmt spien 00000110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xf8
rev. 1.3 231 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 20.3. spi0ckr: spi0 clock rate sfr definition 20.4. spi0dat: spi0 data bits 7?0: scr7?scr0: spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided version of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, r/w r/w r/w r/w r/w r/w r/w r/w reset value scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa2 f sck 2000000 241 + ?? ? f sck 200 khz = f sck sysclk 2 spi 0 ckr 1+ ?? ? bits 7?0: spi0dat: spi0 transmit and receive data. the spi0dat register is used to transmit an d receive spi0 data. writing data to spi0dat places the data into the transmit buffer and in itiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa3
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 232 rev. 1.3 figure 20.8. spi master timing (ckpha = 0) figure 20.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis
rev. 1.3 233 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d figure 20.10. spi slave timing (ckpha = 0) figure 20.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 234 rev. 1.3 table 20.1. spi slave timing parameters parameter description min max units master mode timing* (see figure 20.8 and figure 20.9 ) t mckh sck high time 1 x t sysclk ns t mckl sck low time 1 x t sysclk ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ns t mih sck shift edge to miso change 0 ns slave mode timing* (see figure 20.10 and figure 20.11 ) t se nss falling to first sck edge 2 x t sysclk ns t sd last sck edge to nss rising 2 x t sysclk ns t sez nss falling to miso valid 4 x t sysclk ns t sdz nss rising to miso high-z 4 x t sysclk ns t ckh sck high time 5 x t sysclk ns t ckl sck low time 5 x t sysclk ns t sis mosi valid to sck sample edge 2 x t sysclk ns t sih sck sample edge to mosi change 2 x t sysclk ns t soh sck shift edge to miso change 4 x t sysclk ns t slh last sck edge to mi so change (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns *note: t sysclk is equal to one period of the device system clock (sysclk).
rev. 1.3 235 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 21. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the adc, smbus, usb (frame measure - ments), low-frequency oscillator (p eriod measurement s), or for general purpose use. these timers can be used to measure time intervals, count external events and generate periodic interrupt requests. timer 0 a nd timer 1 are nearly identical and have four primary modes of operation. timer 2 and timer 3 offer 1 6-bit and split 8-bit timer functionality with auto-reload. timers 0 and 1 may be clocked by one of five sour ces, de termined by the timer mode select bits (t1m-t0m) and the clock scale bits (sca1-sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 21.3 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-sc aled clock s ignal or the system clock. timer 2 and t imer 3 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counters. when fun ctioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre - quency of up to one-fourth the system clock's frequen cy can b e counted. the input signal need not be peri - odic, but it should be held at a gi ve n level for at least two full system cl ock cycles to ensure the level is properly sampled. 21.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer co ntrol register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts ca n be enabled by setting the et0 bit in the ie register ( section ?9.3.5. interrupt register descriptions? on page 90 ); timer 1 interrupts can be enabled by setting the et1 bit in the ie register ( section 9.3.5 ). both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1-t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 21.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operat e identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c oun ter/timer. tl0 holds the five lsbs in bit positions tl0.4-tl0.0. the three upper bits of tl0 (tl0.7-tl0 .5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer over flow flag tf0 (tcon.5) is set and an inte rrupt will occur if timer 0 interrupts are enabled. timer 0 and timer 1 modes: ti mer 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload two 8-bit timers with auto-reload two 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 236 rev. 1.3 the c/t0 bit (tmod.2) selects the counter/timer's cloc k source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?15.1. priority crossbar decoder? on page 144 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by th e t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, ti mer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 21.3 ). setting the tr0 bit (tcon.4) enables the timer when ei th er gate0 (tmod.3) is logic 0 or the input signal int0 is active as defined by bit in0pl in register int01cf (see sfr definition 9.13 ). setting gate0 to ?1? allows the timer to be controlled by the external input signal int0 (see section ?9.3.5. interrupt register descriptions? on page 90 ), facilitating pulse width measurements. setting tr0 does not force the timer to reset. the tim er registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal int1 is used with timer 1; the int1 polarity is defined by bit in 1pl in register int01cf (see sfr definition 9.13 ). figure 21.1. t0 mode 0 block diagram 21.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun - ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled x = don't care tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 int0 t0 crossbar int01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor
rev. 1.3 237 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 21.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8- bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload value. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an in terrupt will occur w hen the tf0 flag is set. th e reload value in th0 is not changed. tl0 must be initialized to the desired va lue before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal int0 is active as defined by bit in0pl in register int01cf (see section ?9.3.2. external interrupts? on page 88 for details on the external input signals int0 and int1 ). figure 21.2. t0 mode 2 block diagram tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock int01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 238 rev. 1.3 21.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8- bit counter/timers held in tl0 and th0. the counter/ timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use ei ther the system clock or an external input si gnal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 over flow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operat ing in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud ra tes for the smbus and/or uart, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set - tings. to run timer 1 while timer 0 is in mode 3, set th e timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. figure 21.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 1.3 239 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 21.1. tcon: timer control bit7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 1 interrupt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 0 interrupt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit3: ie1: external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automatically cleare d when the cpu vectors to the external inter- rupt 1 service routine if it1 = 1. when it 1 = 0, this flag is set to ?1? when int1 is active as defined by bit in1pl in register int01cf (see sfr definition 9.13). bit2: it1: interrupt 1 type select. this bit selects whether the configured int1 interrupt will be edge or level sensitive. int1 is configured active low or high by the in1pl bi t in the it01cf register (see sfr definition 9.13). 0: int1 is level triggered. 1: int1 is edge triggered. bit1: ie0: external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can be cleared by software but is automatically cleare d when the cpu vectors to the external inter- rupt 0 service routine if it0 = 1. when it 0 = 0, this flag is set to ?1? when int0 is active as defined by bit in0pl in register int01cf (see sfr definition 9.13). bit0: it0: interrupt 0 type select. this bit selects whether the configured int0 interrupt will be edge or level sensitive. int0 is configured active low or high by the in0pl bi t in register it01cf (see sfr definition 9.13). 0: int0 is level triggered. 1: int0 is edge triggered. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x88
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 240 rev. 1.3 sfr definition 21.2. tmod: timer mode bit7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in register int01cf (see sfr definition 9.13). bit6: c/t1: counter/timer 1 select. 0: timer function: timer 1 incremented by clock defined by t1m bit (ckcon.3). 1: counter function: timer 1 incremented by hi gh-to-low transitions on external input pin (t1). bits5?4: t1m1?t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in register int01cf (see sfr definition 9.13). bit2: c/t0: counter/timer select. 0: timer function: timer 0 incremented by clock defined by t0m bit (ckcon.2). 1: counter function: timer 0 incremented by hi gh-to-low transitions on external input pin (t0). bits1?0: t0m1?t0m0: timer 0 mode select. these bits select the timer 0 operation mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x89 t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 10 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 10 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: two 8-bit counter/timers
rev. 1.3 241 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 21.3. ckcon: clock control bit7: t3mh: timer 3 high byte clock select. this bit selects the clock supplied to the timer 3 high byte if timer 3 is configured in split 8-bit timer mode. t3mh is ignored if timer 3 is in any other mode. 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. bit6: t3ml: timer 3 low byte clock select. this bit selects the clock supplied to timer 3. if timer 3 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. bit5: t2mh: timer 2 high byte clock select. this bit selects the clock supplied to the timer 2 high byte if timer 2 is configured in split 8-bit timer mode. t2mh is ignored if timer 2 is in any other mode. 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. bit4: t2ml: timer 2 low byte clock select. this bit selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. bit3: t1m: timer 1 clock select. this select the clock source supplied to timer 1. t1m is ignored when c/t1 is set to logic 1. 0: timer 1 uses the clock defined by the prescale bits, sca1-sca0. 1: timer 1 uses the system clock. bit2: t0m: timer 0 clock select. this bit selects the clock source supplied to timer 0. t0m is ignored when c/t0 is set to logic 1. 0: counter/timer 0 uses the clock defined by the prescale bits, sca1-sca0. 1: counter/timer 0 uses the system clock. bits1?0: sca1-sca0: time r 0/1 prescale bits. these bits control the division of the clock su pplied to timer 0 and/or timer 1 if configured to use prescaled clock inputs. r/w r/w r/w r/w r/w r/w r/w r/w reset value t3mh t3ml t2mh t2ml t1m t0m sca1 sca0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8e sca1 sca0 prescaled clock 0 0 system clock divided by 12 0 1 system clock divided by 4 1 0 system clock divided by 48 1 1 external clock divided by 8 note: external clock divided by 8 is synchronized with the system clock.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 242 rev. 1.3 sfr definition 21.4. tl0: timer 0 low byte sfr definition 21.5. tl1: timer 1 low byte sfr definition 21.6. th0: timer 0 high byte sfr definition 21.7. th1: timer 1 high byte bits 7?0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8a bits 7?0: tl1: timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x8b bits 7?0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x8c bits 7?0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x8d
rev. 1.3 243 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 21.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, usb start-of-frame (sof) capture mode, or low-frequency os cillator (lfo) falling edge capture mode. the timer 2 operation mode is defined by the t2split (tmr2cn.3), t2ce (tmr2cn.4) bits, and t2css (tmr2cn.1) bits. timer 2 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives the system clock while timer 2 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 21.2.1. 16-bit timer with auto-reload when t2split = ?0? and t2ce = ?0?, timer 2 operates as a 16-bit timer with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is load ed into the timer 2 register as shown in figure 21.4 , and the timer 2 high byte overflow fla g (tmr2cn.7) is set. if timer 2 interrupts are enabled, an interrupt will be generated on each timer 2 ov erflow. additionally, if timer 2 in terrupts are enabled and the tf2len bit is set (tmr2cn.5), an interrupt will be generate d each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 21.4. timer 2 16-bi t mode block diagram external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split t2css t2ce tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 244 rev. 1.3 21.2.2. 8-bit timers with auto-reload when t2split = ?1? and t2ce = ?0?, timer 2 operates as two 8-bit timers (tmr2h and tmr2l). both 8-bit timers operate in auto-reload mode as shown in figure 21.5 . tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 b it in tmr2cn handles t he run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sys clk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2m h and t2ml in ckcon) se lect either sysclk or the clock defined by the timer 2 external cloc k select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00 ; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled, an interrupt is generated each time tmr2h over - flows. if timer 2 interrupts are enabled and tf2len (tm r2cn.5) is set, an interrupt is generated each time either tmr2l or tmr2h overflows. when tf2le n is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 21.5. timer 2 8- bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split t2css t2ce tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 1.3 245 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 21.2.3. timer 2 capture modes: usb start-of-frame or lfo falling edge when t2ce = ?1?, timer 2 will operate in one of two special capture modes. the capture event can be selected between a usb start-of-frame (sof) capture, and a low- frequency oscillator (lfo) falling edge capture, using the t2css bit. the usb sof capt ure mode can be used to calibrate the system clock or external oscillator ag ainst the known usb host sof clock. the lfo falling-edge ca pture mode can be used to calibrate th e internal low-freque ncy oscillator against the internal high-frequency oscillator or an external clock source. when t2split = ?0?, timer 2 counts up and overflows from 0xffff to 0x0000. each time a capture event is received, the contents of the timer 2 registers (tmr2h:tmr2l) are latched in to the timer 2 reload registers (tmr2rlh:tmr2rll). a timer 2 interrupt is generated if enabled. figure 21.6. timer 2 captur e mode (t2split = ?0?) external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh tclk 0 1 tr2 0 1 interrupt ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m capture usb start-of-frame (sof) enable tmr2cn t f 2 h t f 2 l t 2 x c l k t 2 c s s t r 2 t f 2 l e n t 2 c e t 2 s p l i t 0 1 t2css low-frequency oscillator falling edge to adc, smbus to smbus tl2 overflow
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 246 rev. 1.3 when t2split = ?1?, the timer 2 registers (tmr2h and tmr2l) act as two 8-bit counters. each counter cou nts up independently and overflows from 0xff to 0x00. each time a capture event is received, the con - tents of the timer 2 registers are latched into the timer 2 reload registers (tmr2rlh and tmr2rll). a t imer 2 interrupt is generated if enabled. figure 21.7. timer 2 captur e mode (t2split = ?1?) sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 1 0 tmr2h tmr2rlh tclk tmr2l tmr2rll to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2cn t f 2 h t f 2 l t 2 x c l k t 2 c s s t r 2 t f 2 l e n t 2 c e t 2 s p l i t capture enable capture interrupt usb start-of-frame (sof) low-frequency oscillator falling edge 0 1 t2css
rev. 1.3 247 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 21.8. tmr2cn: timer 2 control bit7: tf2h: timer 2 high byte overflow flag. set by hardware when the timer 2 high byte ov erflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0xff ff to 0x0000. when the timer 2 inte rrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. tf2h is not automatically cleared by hard ware and must be cleared by software. bit6: tf2l: timer 2 low byte overflow flag. set by hardware when the timer 2 low byte over flows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf2len is set and timer 2 interr upts are enabled. tf2l will set when the low byte overfl ows regardless of the timer 2 mo de. this bit is not automat- ically cleared by hardware. bit5: tf2len: timer 2 low byte interrupt enable. this bit enables/disables timer 2 low byte in terrupts. if tf2len is set and timer 2 inter- rupts are enabled, an interrupt w ill be generated when the low byte of timer 2 overflows. 0: timer 2 low byte interrupts disabled. 1: timer 2 low byte interrupts enabled. bit4: t2ce: timer 2 capture enable 0: capture function disabled. 1: capture function enabled. the timer is in capture mode, with th e capture event selected by bit t2css. each time a capture event is re ceived, the contents of the timer 2 registers (tmr2h and tmr2l) are latched into the timer 2 reload registers (tmr2rlh and tmr2rlh), and a timer 2 interrupt is generated (if enabled). bit3: t2split: timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. bit2: tr2: timer 2 run control. this bit enables/disables timer 2. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is always enabled in this mode. 0: timer 2 disabled. 1: timer 2 enabled. bit1: t2css: timer 2 capture source select. this bit selects the source of a capture event when bit t2ce is set to ?1?. 0: capture source is usb sof event. 1: capture source is falling ed ge of low-frequen cy oscillator. bit0: t2xclk: timer 2 ex ternal clock select. this bit selects the external clock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external osc illator clock source for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 external clock selection is the system clock divided by 12. 1: timer 2 external clock selection is the external clock divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf2h tf2l tf2len t2ce t2split tr2 t2css t2xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xc8
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 248 rev. 1.3 sfr definition 21.9. tmr2rll: timer 2 relo ad register low byte sfr definition 21.10. tmr2rlh: timer 2 relo ad register high byte sfr definition 21.11. tmr2l: timer 2 low byte sfr definition 21.12. tmr2h timer 2 high byte bits 7?0: tmr2rll: timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2 when operating in auto-reload mode, or the captured value of the tmr2l register in capture mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xca bits 7?0: tmr2rlh: timer 2 reload register high byte. the tmr2rlh holds the high byte of the reload value for timer 2 when operating in auto-reload mode, or the captured value of the tmr2h register in capture mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcb bits 7?0: tmr2l: timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit mode, tmr2l contains the 8-bit low byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcc bits 7?0: tmr2h: timer 2 high byte. in 16-bit mode, the tmr2h register contains t he high byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xcd
rev. 1.3 249 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 21.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, usb start-of-frame (sof) capture mode, or low-frequency os cillator (lfo) rising edge capture mode. the timer 3 operation mode is defined by the t3split (tmr3cn.3), t3ce (tmr3cn.4) bits, and t3css (tmr3cn.1) bits. timer 3 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives the system clock while timer 3 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 21.3.1. 16-bit timer with auto-reload when t3split (tmr3cn.3) is ?0? an d t3ce = ?0?, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the external oscilla tor clock source divided by 8. as the 16-bit timer register increments and ov erflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tm3rll) is loaded into the timer 3 register as shown in figure 21.4 , and the timer 3 high byte overflow flag (tmr3cn.7) is set. if timer 3 interrupts are enabled, an interrupt will be ge nerated on each t imer 3 overflow. additiona lly, if timer 3 interrupts are enabled and the tf3len bit is set (tmr3cn.5), an interrupt will be gener ated each time the lowe r 8 bits (tmr3l) over - flow from 0xff to 0x00. figure 21.8. timer 3 16-bi t mode block diagram external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split t3css t3ce tf3l tf3h t3xclk tr3 0 1 t3xclk interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 250 rev. 1.3 21.3.2. 8-bit timers with auto-reload when t3split is ?1? and t3ce = ?0?, timer 3 operates as two 8-bit timers (tmr3h and tmr3l). both 8-bit timers operate in auto-reload mode as shown in figure 21.5 . tmr3rll holds the reload value for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr3 b it in tmr3cn handles t he run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sys clk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 3 clock select bits (t3m h and t3ml in ckcon) se lect either sysclk or the clock defined by the timer 3 external cloc k select bit (t3xclk in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00 ; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over - flows. if timer 3 interrupts are enabled and tf3len (tm r3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 21.9. timer 3 8- bit mode block diagram t3mh t3xclk tmr3h clock source t3ml t3xclk tmr3l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 t3xclk 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split t3css t3ce tf3len tf3l tf3h t3xclk tr3 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m to adc
rev. 1.3 251 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 21.3.3. usb start-of-frame capture when t3ce = ?1?, timer 3 will operate in one of two special capture modes. the capture event can be selected between a usb st art-of-frame (sof) captur e, and a low-fr equency oscillator (lfo) rising edge capture, using the t3css bit. the usb sof capt ure mode can be used to calibrate the system clock or external oscillator against the known usb host sof clock. the lfo rising- edge capture mode can be used to calibrate th e internal low-freque ncy oscillator against the internal high-frequency oscillator or an external clock source. when t3split = ?0?, timer 3 counts up and overflows from 0xffff to 0x0000. each time a capture event is received, the contents of the timer 3 registers (tmr3h:tmr3l) are latched into the timer 3 reload registers (tmr3rlh:tmr3rll). a timer 3 interrupt is generated if enabled. figure 21.10. time r 3 capture mode (t3split = ?0?) external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh tclk 0 1 tr3 0 1 interrupt to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m capture enable tmr3cn t f 3 h t f 3 l t 3 x c l k t 3 c s s t r 3 t f 3 l e n t 3 c e t 3 s p l i t usb start-of-frame (sof) 0 1 t3css low-frequency oscillator falling edge
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 252 rev. 1.3 when t3split = ?1?, the timer 3 registers (tmr3h and tmr3l) act as two 8-bit counters. each counter cou nts up independently and overflows from 0xff to 0x00. each time a capture event is received, the con - tents of the timer 3 registers are latched into the timer 3 reload registers (tmr3rlh and tmr3rll). a t imer 3 interrupt is generated if enabled. figure 21.11. timer 3 captur e mode (t3split = ?1?) sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 1 0 tmr3h tmr3rlh tclk tmr3l tmr3rll to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3cn t f 3 h t f 3 l t 3 x c l k t 3 c s s t r 3 t f 3 l e n t 3 c e t 3 s p l i t capture enable capture interrupt usb start-of-frame (sof) low-frequency oscillator falling edge 0 1 t3css
rev. 1.3 253 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 21.13. tmr3cn: timer 3 control bit7: tf3h: timer 3 high byte overflow flag. set by hardware when the timer 3 high byte ov erflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0xff ff to 0x0000. when the timer 3 inte rrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. tf3h is not automatically cleared by hard ware and must be cleared by software. bit6: tf3l: timer 3 low byte overflow flag. set by hardware when the timer 3 low byte over flows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf3len is set and timer 3 interr upts are enabled. tf3l will set when the low byte overfl ows regardless of the timer 3 mo de. this bit is not automat- ically cleared by hardware. bit5: tf3len: timer 3 low byte interrupt enable. this bit enables/disables timer 3 low byte in terrupts. if tf3len is set and timer 3 inter- rupts are enabled, an interrupt w ill be generated when the low byte of timer 3 overflows. this bit should be cleared when operating timer 3 in 16-bit mode. 0: timer 3 low byte interrupts disabled. 1: timer 3 low byte interrupts enabled. bit4: t3ce: timer 3 capture enable 0: capture function disabled. 1: capture function enabled. the timer is in capture mode, with th e capture event selected by bit t3css. each time a capture event is re ceived, the contents of the timer 3 registers (tmr3h and tmr3l) are latched into the timer 3 reload registers (tmr3rlh and tmr3rlh), and a timer 3 interrupt is generated (if enabled). bit3: t3split: timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bit auto-reload timers. bit2: tr3: timer 3 run control. this bit enables/disables timer 3. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is always enabled in this mode. 0: timer 3 disabled. 1: timer 3 enabled. bit1: t3css: timer 3 capture source select. this bit selects the source of a capture event when bit t3ce is set to ?1?. 0: capture source is usb sof event. 1: capture source is rising ed ge of low-frequency oscillator. bit0: t3xclk: timer 3 ex ternal clock select. this bit selects the external clock source for timer 3. if timer 3 is in 8-bit mode, this bit selects the external osc illator clock source for both timer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 3 external clock selection is the system clock divided by 12. 1: timer 3 external clock selection is the external clock divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf3h tf3l tf3len t3ce t3split tr3 t3css t3xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x91
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 254 rev. 1.3 sfr definition 21.14. tmr3rll: timer 3 reload register low byte sfr definition 21.15. tmr3rlh: timer 3 relo ad register high byte sfr definition 21.16. tmr3l: timer 3 low byte sfr definition 21.17. tmr3h timer 3 high byte bits 7?0: tmr3rll: timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3 when operating in auto-reload mode, or the captured value of the tmr3l register when operating in capture mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x92 bits 7?0: tmr3rlh: timer 3 reload register high byte. the tmr3rlh holds the high byte of the reload value for timer 3 when operating in auto-reload mode, or the captured value of th e tmr3h register when operating in capture mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x93 bits 7?0: tmr3l: timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x94 bits 7?0: tmr3h: timer 3 high byte. in 16-bit mode, the tmr3h register contains t he high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x95
rev. 1.3 255 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 22. programmable counter array (pca0) the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. each c apture/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled (see section ?15.1. priority crossbar decoder? on page 144 for details on configuring the crossbar). the counter/timer is driven by a programmable timebase that can select between six so urc es: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, timer 0 overflow, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre - quency output, 8-bit pwm, or 16-b it pwm (e ach mode is described in section ?22.2. capture/compare modules? on page 257 ). the external oscillator clock option is i deal for real-time clock (rtc) functionality, allowing the pca to be clocked by a precis ion external oscill ator while the internal oscillator drives the sys - tem clock. the pca is configured and controlled th ro ugh the system controller's special function regis - ters. the pca block diagram is shown in figure 22.1 important note: the pca module 4 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca regi sters is restricted while wdt mode is enabled. see section 22.3 for details. figure 22.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 capture/compare module 4 / wdt cex1 eci crossbar cex2 cex3 cex4 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 256 rev. 1.3 22.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the low byte (lsb). reading pca0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counte r operation. the cps2-cps0 bits in the pca0md register select the timebase for the counter/timer as shown in ta b l e 22.1 . when the counter/timer overflows from 0xffff to 0x0 000 , the counter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the in terrupt service routine, and must be cleared by soft - ware (note: pca0 interrupts must be globally enabled before cf interrupts are recognized. pca0 inter - rupts are globally enabled by setting the ea bit (ie.7) an d the epca0 bit in eie1 to logic 1). clearing the cidl bit in the pca0md register a llows the pca to continue normal operation while the cpu is in idle mode. figure 22.2. pca counter /timer block diagram table 22.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 100system clock 1 0 1 external oscillator source divided by 8* *note: external oscillator source divided by 8 is synchronized with the system clock. pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8
rev. 1.3 257 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 22.2. capture/compare modules each module can be configured to operate independen tly in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. each module has special functi on registers (sfrs) associated with it in the cip-51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. ta b l e 22.2 summarizes the bit settings in the pca0cpmn r egisters used to select the pca capture/com - pare module?s operating modes. setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. note: pca0 interrupts must be globally enabled before individual ccfn interrupts are rec - ognized. pca0 interrupts are globally enabled by se tting the ea bit and the epca0 bit to logic 1. see figure 22.3 for details on the pca interrupt configuration. figure 22.3. pca interrupt block diagram table 22.2. pca0cpm register settings fo r pca capture/comp are modules pwm16 ecom capp capn mat tog pwm eccf operation mode x x 10000x capture triggered by positive edge on cexn x x 01000x capture triggered by negative edge on cexn x x 1 1 0 0 0 x capture triggered by transition on cexn x 1 0 0 1 0 0 x software timer x 1 0 0 1 1 0 x high speed output x 1 0 0 x 1 1 x frequency output 0 1 0 0 x 0 1 x 8-bit pulse width modulator 1 1 0 0 x 0 1 x 16-bit pulse width modulator x = don?t care pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 0 1 pca module 3 (ccf3) eccf3 0 1 pca module 4 (ccf4) eccf4 pca counter/ timer overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 4) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 258 rev. 1.3 22.2.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture th e value of the pca counter/ timer and load it into the corresponding module' s 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi - tion that triggers the capture: low-to-high transition (p o sitive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when th e cpu vectors to the interrupt serv ice routine, and must be cleared by software . if both cappn and capnn bi ts are set to logic 1, t hen the state of the port pin associated with cexn can be read directly to de termine whether a rising-edge or falling-edge caused the capture. figure 22.4. pca capture mode diagram note: the cexn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt 0 000x x
rev. 1.3 259 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 22.2.2. software timer (compare) mode in software timer mode, the pca counter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not autom atically cleared by ha rdware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. figure 22.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 260 rev. 1.3 22.2.3. high speed output mode in high speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln) setting the togn, matn, and ecomn bi ts in the pca0cpmn register enables the high-speed output mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. figure 22.6. pca high speed output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt
rev. 1.3 261 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 22.2.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out - put is toggled. the frequency of the square wave is then defined by equation 22.1 . equation 22.1. square wave fr equency output where f pca is the frequency of the clock selected by the cps2-0 bits in the pca mode register, pca0md. the lower byte of the capture/compare module is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the high by te is added to the matched value in pca0cpln. fre - quency output mode is enabled by setting the ecom n, t ogn, and pwmn bits in the pca0cpmn register. figure 22.7. pca frequency output mode f cexn f pca 2 pca0 cphn ? note: a value of 0x00 in the pca0cphn re gister is equal to 256 for this equation. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 262 rev. 1.3 22.2.5. 8-bit pulse width modulator mode each module can be used independently to generate a pulse width modulated (pwm) output on its associ - ated cexn pin. the frequency of the output is depe nde nt on the timebase for the pca counter/timer. the duty cycle of the pwm output signal is varied usin g the module's pca0cpln capture/compare register. when the value in the low byte of the pca counter/ti mer (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be set. when the count value in pca0l ov erflows, the cexn output will be reset (see figure 22.8 ). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value sto red in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register enables 8-bit pulse width modulator mode. the duty cycle for 8-bit pwm mode is given by equation 22.2 . important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. equation 22.2. 8-bit pwm duty cycle using equation 22.2 , the largest duty cycle is 100% (pca0cph n = 0 ), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be g enerated by clearing the ecomn bit to ?0?. figure 22.8. pca 8-bi t pwm mode diagram dutycycle 256 pca0 cphn ? ?? 256 ----------------------------------- ---------------- = 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset
rev. 1.3 263 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 22.2.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. in this mode, the 16-bit capture/compare mod - ule defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the output on cexn is asserted high; when the counter overfl ows, cexn is asserted low. to output a varying duty cycle, new value writ es should be synchronized with pca ccfn match inter - rupts. 16-bit pwm mode is enabled by setting the ecom n, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compare register writes. the duty cycle for 16-bit pwm mode is given by equation 22.3 . important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. equation 22.3. 16-bit pwm duty cycle using equation 22.3 , the largest duty cycle is 100% (pca0cpn = 0) , and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. figure 22.9. pca 16-bit pwm mode dutycycle 65536 pca0 cpn ? ?? 65536 ---------------------------------------------------- - = pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 264 rev. 1.3 22.3. watchdog timer mode a programmable watchdog timer (wdt) function is avai lable through the pca module 4. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph4) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte and/or wdlck bits set to ?1? in t he pca0m d register, module 4 operates as a watchdog timer (wdt). the module 4 high byte is compared to the pca counter high byte; the module 4 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. 22.3.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2-cps0) are frozen. ? pca idle control bit (cidl) is frozen. ? module 4 is forced into watchdog timer mode. ? writes to the module 4 mode re g ister (pca0cpm4) are disabled. while the wdt is enabled, writes to the cr bit will not c hange the pca counter state; the counter will run until the wdt is disabled. the pca co unter run cont rol (cr) will read zero if the wdt is enabled but user software has not enabled the pca counter. if a ma tch occurs between pca0cph4 and pca0h while the wdt is enabled, a reset will be gener ated. to prevent a wdt reset, the wdt may be updated with a write of any value to pca0cph4. upon a pca0cph4 write, pca0h plus the offset held in pca0cpl4 is loaded into pca0cph4 (see figure 22.10 ). figure 22.10. pca module 4 wi th watchdog timer enabled note that the 8-bit offset held in pca0cph4 is comp ared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the valu e of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 22.4 , where pca0l is the value of the pca0l register at the time of the update. pca0h enable pca0l overflow reset pca0cpl4 8-bit adder pca0cph4 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph4 8-bit comparator
rev. 1.3 265 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d equation 22.4. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph4 and pca0h. software may force a wdt reset by writing a ?1? to the ccf4 flag (pca0cn.4) while the wdt is enabled. 22.3.2. watchdog timer usage to configure the wdt, perform the following tasks: 1. disable the wdt by writing a ?0? to the wdte bit. 2. select the desired pca clock s our ce (with the cps2-cps0 bits). 3. load pca0cpl4 with the de sir ed wdt update offset value. 4. configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). 5. enable the wdt by setting the wdte bit to ?1?. 6. (optional) lock the wdt (prevent wdt disabl e until t he next system reset) by setting the wdlck bit to ?1?. 7. write a value to pca0cph4 to reload the wdt. ? the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any reset. the pca0 c oun ter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl4 defaults to 0x00. using equation 22.4 , this results in a wdt timeout interval of 256 pca clocks. table 22.3 lists some example timeout intervals for typical system clocks. table 22.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl4 timeout interval (ms) 12,000,000 255 65.5 12,000,000 128 33.0 12,000,000 32 8.4 24,000,000 255 32.8 24,000,000 128 16.5 24,000,000 32 4.2 1,500,000 2 255 524.3 1,500,000 2 128 264.2 1,500,000 2 32 67.6 32,768 255 24,000 32,768 128 12,093.75 32,768 32 3,093.75 notes: 1. assumes sysclk / 12 as the pc a clock source, and a pca0l value of 0x00 at the update time. 2. syste m clock reset frequency. offset 256 pca0 cpl4 ? ?? 256 pca0 l ? ?? + =
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 266 rev. 1.3 22.4. register descriptions for pca following are detailed descriptions of the special function registers related to the operation of the pca. sfr definition 22.1. pca0cn: pca control bit7: cf: pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) inte rrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bi t is not automatically cleared by hardware and must be cleared by software. bit6: cr: pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. bit5: unused. read = 0b, write = don't care. bit4: ccf4: pca module 4 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf4 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit3: ccf3: pca module 3 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf3 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit2: ccf2: pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf2 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit1: ccf1: pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf1 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit0: ccf0: pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf0 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd8
rev. 1.3 267 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 22.2. pca0md: pca mode bit7: cidl: pca counter/timer idle control. specifies pca behavior wh en cpu is in idle mode. 0: pca continues to function normally while the system controller is in idle mode. 1: pca operation is suspended while the system controller is in idle mode. bit6: wdte: watchdog timer enable if this bit is set, pca module 4 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 4 enabled as watchdog timer. bit5: wdlck: watchdog timer lock this bit enables and locks the watchdog timer. when wdlck is set to ?1?, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer unlocked. 1: watchdog timer enabled and locked. bit4: unused. read = 0b, write = don't care. bits3?1: cps2?cps0: pca coun ter/timer pulse select. these bits select the timebase source for the pca counter . bit0: ecf: pca counter/timer overflow interrupt enable. this bit sets the masking of the pca counter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow interrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to ?1?, the pca0 md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value cidl wdte wdlck - cps2 cps1 cps0 ecf 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd9 cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external clock divided by 8* 1 1 0 reserved 1 1 1 reserved *note: external oscillator source divided by 8 is synchronized with the system clock.
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 268 rev. 1.3 sfr definition 22.3. pca0cpmn: pca capture/compare mode pca0cpmn address: pca0cpm0 = 0xda (n = 0), pca0cpm1 = 0xdb (n = 1), pca0cpm2 = 0xdc (n = 2), pca0cpm3 = 0xdd (n = 3), pca0cpm4 = 0xde (n = 4) bit7: pwm16n: 16-bit pulse width modulation enable. this bit selects 16-bit mode when pulse width modulation mode is enabled (pwmn = 1). 0: 8-bit pwm selected. 1: 16-bit pwm selected. bit6: ecomn: comparator function enable. this bit enables/disables the comp arator function for pca module n. 0: disabled. 1: enabled. bit5: cappn: capture positi ve function enable. this bit enables/disables the positive edge capture for pca module n. 0: disabled. 1: enabled. bit4: capnn: capture negative function enable. this bit enables/disables the negative edge capture for pca module n. 0: disabled. 1: enabled. bit3: matn: match function enable. this bit enables/disables the match function for pca module n. when enabled, matches of the pca counter with a module's capture/comp are register cause the ccfn bit in pca0md register to be set to logic 1. 0: disabled. 1: enabled. bit2: togn: toggle function enable. this bit enables/disables the toggle function for pca module n. when enabled, matches of the pca counter with a module's capture/comp are register cause the logic level on the cexn pin to toggle. if the pwmn bit is also set to logic 1, the module operates in frequency output mode. 0: disabled. 1: enabled. bit1: pwmn: pulse width modulation mode enable. this bit enables/disables the pwm function for pca module n. when enabled, a pulse width modulated signal is output on the cexn pin. 8-bi t pwm is used if pwm16n is cleared; 16-bit mode is used if pwm16n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0: disabled. 1: enabled. bit0: eccfn: capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. r/w r/w r/w r/w r/w r/w r/w r/w reset value pwm16n ecomn cappn capnn matn togn pwmn eccfn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xda, 0xdb, 0xdc, 0xdd, 0xde
rev. 1.3 269 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d sfr definition 22.4. pca0l: pca counter/timer low byte sfr definition 22.5. pca0h: pca counter /t imer high byte sfr definition 22.6. pca0cpln: pca capture module low byte bits 7?0: pca0l: pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf9 bits 7?0: pca0h: pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfa pca0cpln address: pca0cpl0 = 0xfb (n = 0), pca0cpl1 = 0xe9 (n = 1), pca0cpl2 = 0xeb (n = 2), pca0cpl3 = 0xed (n = 3), pca0cpl4 = 0xfd (n = 4) bits7?0: pca0cpln: pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfb, 0xe9, 0xeb, 0xed, 0xfd
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 270 rev. 1.3 sfr definition 22.7. pca0cphn: pca captur e module high byte pca0cphn address: pca0cph0 = 0xfc (n = 0), pca0cph1 = 0xea (n = 1), pca0cph2 = 0xec (n = 2), pca0cph3 = 0xee (n = 3), pca0cph4 = 0xfe (n = 4) bits7?0: pca0cphn: pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. r/wr/wr/wr/wr/wr/wr/wr/wreset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xfc, 0xea, 0xec,0xee, 0xfe
rev. 1.3 271 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 23. c2 interface c8051f34x devices include an on-chi p silicon labs 2-wire (c2) debug interface to allow flash program - ming and in-system debugging with the production part in stalled in the end application. the c2 interface uses a clock signal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a host system. see the c2 interface specification for details on the c2 protocol. 23.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming functions through the c2 interface. all c2 registers are accessed through the c2 interface as described in the c2 interface spec - ification. c2 register definition 23.1. c2add: c2 address c2 register definition 23.2. deviceid: c2 device id bits7?0: the c2add register is accessed via the c2 interface to select the ta rget data register for c2 data read and data write commands. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id regist er for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xad selects the c2 flash programming data register for data read/write instructions this read-only register returns the 8-bit device id: 0x0f (c8051f340/1/2 /3/4/5/6/7/8 /9/a/b/c/d). reset value 00001111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 272 rev. 1.3 c2 register definition 23.3. revid: c2 revision id c2 register definition 23.4. fpctl: c2 flash programming control c2 register definition 23.5. fpdat: c2 flash programming data this read-only register returns the 8-bit revision id. reset value variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bits7?0 fpctl: flash programming control register. this register is used to enable flash programmi ng via the c2 interface. to enable c2 flash programming, the following codes must be writte n in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset mu st be issued to resume normal operation. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bits7?0: fpdat: c2 flash programming data register. this register is used to pass flash comma nds, addresses, and data during c2 flash accesses. valid commands are listed below. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
rev. 1.3 273 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 23.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming functions may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely ?borrow? the c2ck ( rst ) and c2d (p3.0) pins. note that the c2d pin is shared on the 32-pin packages only (c8051f342/3/6/7/9/a/b). in most applications, exter - nal resistors are required to isolate c2 interface traffi c fr om the user application. a typical isolation configu - ration is shown in figure 23.1 . figure 23.1. typical c2 pin sharing the configuration in figure 23.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck rst (a) input (b) output (c) c2 interface master c8051fxxx
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 274 rev. 1.3 d ocument c hange l ist revision 0.5 to revision 1.0 ? updated ta b l e 3.1, ?global dc electrical ch aracteristics,? on page 25 . ? updated ta b l e 5.1, ?adc0 electrical ch ar acteristics,? on page 56 . ? various small text changes. ? updated ta b l e 8.1, ?voltage regulator electrical specifications,? on page 69 . ? updated flash security behavior. revision 1.0 to revision 1.1 ? added two new part numbers c8051f348/9 and made associated changes. ? corrected the entries "24 khz" and "48 khz" to "2 4 mhz" and "48 mhz" in the "conditions" column of table 3.1, "global dc electric al characteristics," on page 38. ? added note to configure external inte r rupt pin as open-drain with a ?1? in the port latch in section 9.3.2. "external interrupts" on page 96. ? various small text changes. ? updated the figures in section 15.1. "priority cros sba r decoder" and added a new figure to clarify crossbar capabilities. ? corrected the description of the un drun bit in usb register de finition 16.19. "eincsrl: usb0 in endpoint control low byte" on page 198 to clarif y that this bit works only in isochronous mode. ? corrected the maximum smbus speed from 1/10th to 1/20th of the system clock in section 17. "smbus" on page 205. ? corrected the descriptions for the following states a nd the corresponding typical response options in table 17.4. "smbus status decoding" on page 221: - slave transmitter (status vector: 0101) - slave receiver (status vector: 0001) ? corrected the bit location of msten from spi0cn. 6 to spi 0cfg.6 in section 20.2. "spi0 master operation" on page 243. ? corrected the description of the wcol bit in sfr definitio n 20.2. "spi0cn: spi0 control" on page 249 to match the description in section 20. 4. "spi0 interrupt sources" on page 245. ? clarified the following parameters in ta b l e 8.1, ?voltage regulator electrical specifications,? on page 69: - vbus detection input high and low voltages - dropout voltage ? updated the package drawings with ad d itional dimensions in figure 4.2 and ta b l e 4.2, ?tqfp-48 package dimensions,? on page 32 , and figure 4.4 and ta b l e 4.4, ?lqfp-32 package dimensions,? on page 35. revision 1.1 to revision 1.2 ? added two new part numbers c8051f34a/b and made associated changes. ? corrected references to locations of t0m and t1m in the sfr definition of tmod on page 240 . ? corrected instances of "8k" to "4k" in t he sfr definition of emi0cf on page 118 . revision 1.2 to revision 1.3 ? added qfn-32 package. revision 1.3 to revision 1.4 ? added c8051f34c and c8051f34d devices.
rev. 1.3 275 c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d n otes :
c8051f340/1/2/3/4/5/6/7/8/9/a/b/c/d 276 rev. 1.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez ? austin, tx 78701 ? tel: 1+(512) 416-8500 ? fax: 1+(512) 416-9669 ? toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page ? and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brand names mentioned herein are trademark s or registered trademarks of their respective holders the information in this document is believed to be accurate in al l respects at the time of public ation but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. addition ally, silicon laboratories assume s no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make changes wi thout further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assu me any liability arising out of the applicati on or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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